A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.
|Publication status||Published - 1989|
|Event||19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany|
Duration: 11 Sep 1989 → 14 Sep 1989
Conference number: 19
|Conference||19th European Solid State Device Research Conference, ESSDERC 1989|
|Period||11/09/89 → 14/09/89|
Warmerdam, L. F. P., Aarnink, A. A. I., Holleman, J., & Wallinga, H. (1989). A self-aligned gate definition process with submicron gaps. 37-40. Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.