A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam; A.A.I. Aarnink; J. Holleman; Hans Wallinga

doi:10.1007/978-3-642-52314-4_6

A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam, A.A.I. Aarnink, J. Holleman, Hans Wallinga

Research output: Contribution to conference › Paper

1 Citation (Scopus)

277 Downloads (Pure)

Abstract

A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

Original language	English
Pages	37-40
DOIs	https://doi.org/10.1007/978-3-642-52314-4_6
Publication status	Published - 1989
Event	19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany Duration: 11 Sept 1989 → 14 Sept 1989 Conference number: 19

Conference

Conference	19th European Solid State Device Research Conference, ESSDERC 1989
Abbreviated title	ESSDERC
Country/Territory	Germany
City	Berlin
Period	11/09/89 → 14/09/89

Keywords

n/a OA procedure

Access to Document

10.1007/978-3-642-52314-4_6

ArticleFinal published version, 993 KB

Cite this

@conference{ddee4641bb4f4326b65a7ff41f2cadcb,

title = "A self-aligned gate definition process with submicron gaps",

abstract = "A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.",

keywords = "n/a OA procedure",

author = "L.F.P. Warmerdam and A.A.I. Aarnink and J. Holleman and Hans Wallinga",

year = "1989",

doi = "10.1007/978-3-642-52314-4_6",

language = "English",

pages = "37--40",

note = "19th European Solid State Device Research Conference, ESSDERC 1989, ESSDERC ; Conference date: 11-09-1989 Through 14-09-1989",

}

TY - CONF

T1 - A self-aligned gate definition process with submicron gaps

AU - Warmerdam, L.F.P.

AU - Aarnink, A.A.I.

AU - Holleman, J.

AU - Wallinga, Hans

N1 - Conference code: 19

PY - 1989

Y1 - 1989

N2 - A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

AB - A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

KW - n/a OA procedure

U2 - 10.1007/978-3-642-52314-4_6

DO - 10.1007/978-3-642-52314-4_6

M3 - Paper

SP - 37

EP - 40

T2 - 19th European Solid State Device Research Conference, ESSDERC 1989

Y2 - 11 September 1989 through 14 September 1989

ER -

A self-aligned gate definition process with submicron gaps

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this