A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam, Antonius A.I. Aarnink, J. Holleman, Hans Wallinga

    Research output: Contribution to conferencePaper

    1 Citation (Scopus)
    49 Downloads (Pure)

    Abstract

    A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.
    Original languageUndefined
    Pages37-40
    Publication statusPublished - 1989
    Event19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany
    Duration: 11 Sep 198914 Sep 1989
    Conference number: 19

    Conference

    Conference19th European Solid State Device Research Conference, ESSDERC 1989
    Abbreviated titleESSDERC
    CountryGermany
    CityBerlin
    Period11/09/8914/09/89

    Keywords

    • IR-96394

    Cite this

    Warmerdam, L. F. P., Aarnink, A. A. I., Holleman, J., & Wallinga, H. (1989). A self-aligned gate definition process with submicron gaps. 37-40. Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.