A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam, Antonius A.I. Aarnink, J. Holleman, Hans Wallinga

Research output: Contribution to conferencePaperAcademic

1 Citation (Scopus)
26 Downloads (Pure)

Abstract

A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.
Original languageUndefined
Pages37-40
Publication statusPublished - 1989
Event19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany
Duration: 11 Sep 198914 Sep 1989
Conference number: 19

Conference

Conference19th European Solid State Device Research Conference, ESSDERC 1989
Abbreviated titleESSDERC
CountryGermany
CityBerlin
Period11/09/8914/09/89

Keywords

  • IR-96394

Cite this

Warmerdam, L. F. P., Aarnink, A. A. I., Holleman, J., & Wallinga, H. (1989). A self-aligned gate definition process with submicron gaps. 37-40. Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.
Warmerdam, L.F.P. ; Aarnink, Antonius A.I. ; Holleman, J. ; Wallinga, Hans. / A self-aligned gate definition process with submicron gaps. Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.
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Warmerdam, LFP, Aarnink, AAI, Holleman, J & Wallinga, H 1989, 'A self-aligned gate definition process with submicron gaps' Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany, 11/09/89 - 14/09/89, pp. 37-40.

A self-aligned gate definition process with submicron gaps. / Warmerdam, L.F.P.; Aarnink, Antonius A.I.; Holleman, J.; Wallinga, Hans.

1989. 37-40 Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.

Research output: Contribution to conferencePaperAcademic

TY - CONF

T1 - A self-aligned gate definition process with submicron gaps

AU - Warmerdam, L.F.P.

AU - Aarnink, Antonius A.I.

AU - Holleman, J.

AU - Wallinga, Hans

PY - 1989

Y1 - 1989

N2 - A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

AB - A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

KW - IR-96394

M3 - Paper

SP - 37

EP - 40

ER -

Warmerdam LFP, Aarnink AAI, Holleman J, Wallinga H. A self-aligned gate definition process with submicron gaps. 1989. Paper presented at 19th European Solid State Device Research Conference, ESSDERC 1989, Berlin, Germany.