A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam; A.A.I. Aarnink; J. Holleman; Hans Wallinga

doi:10.1007/978-3-642-52314-4_6

A self-aligned gate definition process with submicron gaps

L.F.P. Warmerdam
, A.A.I. Aarnink
, J. Holleman
, Hans Wallinga

Research output: Contribution to conference › Paper

2 Citations (Scopus)

412 Downloads (Pure)

Abstract

A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

Original language	English
Pages	37-40
DOIs	https://doi.org/10.1007/978-3-642-52314-4_6
Publication status	Published - 1989
Event	19th European Solid State Device Research Conference, ESSDERC 1989 - Berlin, Germany Duration: 11 Sept 1989 → 14 Sept 1989 Conference number: 19

Conference

Conference	19th European Solid State Device Research Conference, ESSDERC 1989
Abbreviated title	ESSDERC
Country/Territory	Germany
City	Berlin
Period	11/09/89 → 14/09/89

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n/a OA procedure

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10.1007/978-3-642-52314-4_6

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title = "A self-aligned gate definition process with submicron gaps",

abstract = "A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.",

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AU - Warmerdam, L.F.P.

AU - Aarnink, A.A.I.

AU - Holleman, J.

AU - Wallinga, Hans

N1 - Conference code: 19

PY - 1989

Y1 - 1989

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AB - A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.

KW - n/a OA procedure

U2 - 10.1007/978-3-642-52314-4_6

DO - 10.1007/978-3-642-52314-4_6

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T2 - 19th European Solid State Device Research Conference, ESSDERC 1989

Y2 - 11 September 1989 through 14 September 1989

ER -

A self-aligned gate definition process with submicron gaps

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Conference

Keywords

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