A self-checking cell logic block for fault tolerant FPGAs

S. Pontarelli; G.C. Cardarilli; A. Leandri; M. Ottavi; M. Re; A. Salsano

doi:10.1109/ISCAS.2002.1010496

A self-checking cell logic block for fault tolerant FPGAs

S. Pontarelli
, G.C. Cardarilli
, A. Leandri
, M. Ottavi
, M. Re
, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2002.1010496
Publication status	Published - 2002
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2002 - Scottsdale Princess Resort, Scottsdale, United States Duration: 26 May 2002 → 29 May 2002 http://www.securecms.com/iscas2002/

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2002
Country/Territory	United States
City	Scottsdale
Period	26/05/02 → 29/05/02
Internet address	http://www.securecms.com/iscas2002/

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10.1109/ISCAS.2002.1010496

Cite this

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title = "A self-checking cell logic block for fault tolerant FPGAs",

abstract = "This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.",

author = "S. Pontarelli and G.C. Cardarilli and A. Leandri and M. Ottavi and M. Re and A. Salsano",

year = "2002",

doi = "10.1109/ISCAS.2002.1010496",

language = "English",

isbn = "0-7803-7448-7",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2002 ; Conference date: 26-05-2002 Through 29-05-2002",

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T1 - A self-checking cell logic block for fault tolerant FPGAs

AU - Pontarelli, S.

AU - Cardarilli, G.C.

AU - Leandri, A.

AU - Ottavi, M.

AU - Re, M.

AU - Salsano, A.

PY - 2002

Y1 - 2002

N2 - This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

AB - This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

UR - https://www.scopus.com/pages/publications/0036294930

U2 - 10.1109/ISCAS.2002.1010496

DO - 10.1109/ISCAS.2002.1010496

M3 - Conference contribution

SN - 0-7803-7448-7

BT - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2002

Y2 - 26 May 2002 through 29 May 2002

ER -

A self-checking cell logic block for fault tolerant FPGAs

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