A signed digit adder with error correction and graceful degradation capabilities

G.C. Cardarilli; M. Ottavi; S. Pontarelli; M. Re; A. Salsano

doi:10.1109/OLT.2004.1319672

A signed digit adder with error correction and graceful degradation capabilities

G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry operation is confined to neighbor digits. The usage of a "carry free" adder implies some advantages in terms of error detection, fault localization and repair For the detection standpoint, a parity checker can be easily applied to detect errors caused by faults belonging to the considered stuck-at fault set. Regarding the fault localization, the "carry free" property of the adder ensures the confinement of the error due to a permanent fault only to a few digits. Finally, if a fault is correctly localized, the faulty digit can be excluded and the logic which computes the other digits can be used to perform the adder operation with a reduced dynamic range.

Original language	English
Title of host publication	Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004
DOIs	https://doi.org/10.1109/OLT.2004.1319672
Publication status	Published - 2004
Externally published	Yes
Event	10th IEEE International On-Line Testing Symposium 2004 - Funchal, Portugal Duration: 14 Jul 2004 → 14 Jul 2004 Conference number: 10

Conference

Conference	10th IEEE International On-Line Testing Symposium 2004
Country/Territory	Portugal
City	Funchal
Period	14/07/04 → 14/07/04

Access to Document

10.1109/OLT.2004.1319672

Cite this

@inproceedings{e85b4a02eb96472bb53f315da953146b,

title = "A signed digit adder with error correction and graceful degradation capabilities",

abstract = "This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry operation is confined to neighbor digits. The usage of a {"}carry free{"} adder implies some advantages in terms of error detection, fault localization and repair For the detection standpoint, a parity checker can be easily applied to detect errors caused by faults belonging to the considered stuck-at fault set. Regarding the fault localization, the {"}carry free{"} property of the adder ensures the confinement of the error due to a permanent fault only to a few digits. Finally, if a fault is correctly localized, the faulty digit can be excluded and the logic which computes the other digits can be used to perform the adder operation with a reduced dynamic range.",

author = "G.C. Cardarilli and M. Ottavi and S. Pontarelli and M. Re and A. Salsano",

year = "2004",

doi = "10.1109/OLT.2004.1319672",

language = "English",

booktitle = "Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004",

note = "10th IEEE International On-Line Testing Symposium 2004 ; Conference date: 14-07-2004 Through 14-07-2004",

}

TY - GEN

T1 - A signed digit adder with error correction and graceful degradation capabilities

AU - Cardarilli, G.C.

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Re, M.

AU - Salsano, A.

N1 - Conference code: 10

PY - 2004

Y1 - 2004

N2 - This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry operation is confined to neighbor digits. The usage of a "carry free" adder implies some advantages in terms of error detection, fault localization and repair For the detection standpoint, a parity checker can be easily applied to detect errors caused by faults belonging to the considered stuck-at fault set. Regarding the fault localization, the "carry free" property of the adder ensures the confinement of the error due to a permanent fault only to a few digits. Finally, if a fault is correctly localized, the faulty digit can be excluded and the logic which computes the other digits can be used to perform the adder operation with a reduced dynamic range.

AB - This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry operation is confined to neighbor digits. The usage of a "carry free" adder implies some advantages in terms of error detection, fault localization and repair For the detection standpoint, a parity checker can be easily applied to detect errors caused by faults belonging to the considered stuck-at fault set. Regarding the fault localization, the "carry free" property of the adder ensures the confinement of the error due to a permanent fault only to a few digits. Finally, if a fault is correctly localized, the faulty digit can be excluded and the logic which computes the other digits can be used to perform the adder operation with a reduced dynamic range.

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-10444254623&partnerID=MN8TOARS

U2 - 10.1109/OLT.2004.1319672

DO - 10.1109/OLT.2004.1319672

M3 - Conference contribution

BT - Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

T2 - 10th IEEE International On-Line Testing Symposium 2004

Y2 - 14 July 2004 through 14 July 2004

ER -

A signed digit adder with error correction and graceful degradation capabilities

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this