Abstract
A conventional technique to rise temperature in a processor involves the usage of thermal ovens or infrared techniques to heat up and then measure the temperature of the processor. However, local temperatures of each module cannot be controlled by these techniques. This paper presents a software mechanism to heat-up a processor while the temperature of each modules of the processor can precisely be calculated. In order to develop our mechanism, first a mathematical model to correlate dynamic power and local temperature has been developed; next a framework that calculates local temperature for any given workload has been presented. In order to show the details of our model, the proposed framework has been applied to a thirty-two bit full-adder. The applicability of our framework has been demonstrated by using a complex DSP (Digital Signal Processor) as the case study. This paper will show that, despite common belief, there is no linear correlation between dynamic power and local temperatures of a chip.
Original language | English |
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Pages | 183-188 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2016 |
Event | 26th International Workshop on Power and Timing Modeling, Optimization and Simulation - Bremen, Germany Duration: 21 Sept 2016 → 23 Sept 2016 Conference number: 26 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7813533 |
Conference
Conference | 26th International Workshop on Power and Timing Modeling, Optimization and Simulation |
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Abbreviated title | PATMOS 2016 |
Country/Territory | Germany |
City | Bremen |
Period | 21/09/16 → 23/09/16 |
Internet address |
Keywords
- CMOS logic circuits;adders;circuit CAD;digital signal processing chips;temperature measurement;thermal management (packaging);CMOS processors;DSP;digital signal processor;dynamic power-local temperature correlation;infrared techniques;local temperature calculation;mathematical model;software mechanism;thermal ovens;thirty-two bit full-adder;Heat transfer;Mathematical model;Numerical models;Resistance heating;Semiconductor device modeling;Thermal resistance;CAD;Processors;Thermal-aware design