Abstract
Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs.
This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application.
Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.
Original language | English |
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Title of host publication | 23rd International Conference on Field Programmable Logic and Applications, FPL2013 |
Place of Publication | USA |
Publisher | IEEE Computer Society |
Pages | 1-2 |
Number of pages | 2 |
ISBN (Print) | 978-1-4799-0004-6 |
DOIs | |
Publication status | Published - 2013 |
Event | 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - HF Ipanema Park, Porto, Portugal Duration: 2 Sep 2013 → 4 Sep 2013 Conference number: 23 |
Conference
Conference | 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 |
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Abbreviated title | FPL |
Country | Portugal |
City | Porto |
Period | 2/09/13 → 4/09/13 |
Keywords
- METIS-300111
- EWI-23877
- FPGAs
- Design Methodology
- IR-87842
- particle filtering