Abstract
Original language | English |
---|---|
Title of host publication | 23rd International Conference on Field Programmable Logic and Applications, FPL2013 |
Place of Publication | USA |
Publisher | IEEE Computer Society |
Pages | 1-2 |
Number of pages | 2 |
ISBN (Print) | 978-1-4799-0004-6 |
DOIs | |
Publication status | Published - 2013 |
Event | 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - HF Ipanema Park, Porto, Portugal Duration: 2 Sep 2013 → 4 Sep 2013 Conference number: 23 |
Conference
Conference | 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 |
---|---|
Abbreviated title | FPL |
Country | Portugal |
City | Porto |
Period | 2/09/13 → 4/09/13 |
Fingerprint
Keywords
- METIS-300111
- EWI-23877
- FPGAs
- Design Methodology
- IR-87842
- particle filtering
Cite this
}
A space/time tradeoff methodology using higher-order functions. / Wester, Rinse; Kuper, Jan.
23rd International Conference on Field Programmable Logic and Applications, FPL2013. USA : IEEE Computer Society, 2013. p. 1-2.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A space/time tradeoff methodology using higher-order functions
AU - Wester, Rinse
AU - Kuper, Jan
N1 - 10.1109/FPL.2013.6645613
PY - 2013
Y1 - 2013
N2 - Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.
AB - Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.
KW - METIS-300111
KW - EWI-23877
KW - FPGAs
KW - Design Methodology
KW - IR-87842
KW - particle filtering
U2 - 10.1109/FPL.2013.6645613
DO - 10.1109/FPL.2013.6645613
M3 - Conference contribution
SN - 978-1-4799-0004-6
SP - 1
EP - 2
BT - 23rd International Conference on Field Programmable Logic and Applications, FPL2013
PB - IEEE Computer Society
CY - USA
ER -