A space/time tradeoff methodology using higher-order functions

Rinse Wester; Jan Kuper

doi:10.1109/FPL.2013.6645613

A space/time tradeoff methodology using higher-order functions

Rinse Wester, Jan Kuper

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.

Original language	English
Title of host publication	23rd International Conference on Field Programmable Logic and Applications, FPL2013
Place of Publication	USA
Publisher	IEEE Computer Society
Pages	1-2
Number of pages	2
ISBN (Print)	978-1-4799-0004-6
DOIs	https://doi.org/10.1109/FPL.2013.6645613
Publication status	Published - 2013
Event	23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - HF Ipanema Park, Porto, Portugal Duration: 2 Sep 2013 → 4 Sep 2013 Conference number: 23

Conference

Conference	23rd International Conference on Field Programmable Logic and Applications, FPL 2013
Abbreviated title	FPL
Country	Portugal
City	Porto
Period	2/09/13 → 4/09/13

Keywords

METIS-300111
EWI-23877
FPGAs
Design Methodology
IR-87842
particle filtering

Access to Document

10.1109/FPL.2013.6645613

http://eprints.eemcs.utwente.nl/secure2/23877/01/FPL2013_Wester.pdf

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Cite this

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title = "A space/time tradeoff methodology using higher-order functions",

abstract = "Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.",

keywords = "METIS-300111, EWI-23877, FPGAs, Design Methodology, IR-87842, particle filtering",

author = "Rinse Wester and Jan Kuper",

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AB - Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.

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KW - EWI-23877

KW - FPGAs

KW - Design Methodology

KW - IR-87842

KW - particle filtering

U2 - 10.1109/FPL.2013.6645613

DO - 10.1109/FPL.2013.6645613

M3 - Conference contribution

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