A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

Anne J. Annema; P. Veldhorst; G Doornbos; Bram Nauta

doi:10.1109/ISSCC.2009.4977443

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

Anne J. Annema, P. Veldhorst, G Doornbos, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

26 Citations (Scopus)

91 Downloads (Pure)

Abstract

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference
Place of Publication	Piscataway
Publisher	IEEE Computer Society Press
Pages	332-333
Number of pages	2
ISBN (Print)	978-1-4244-3458-9
DOIs	https://doi.org/10.1109/ISSCC.2009.4977443
Publication status	Published - 8 Feb 2009
Event	IEEE International Solid-State Circuits Conference, ISSCC 2009 - San Francisco, United States Duration: 8 Feb 2009 → 12 Feb 2009

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2009
Abbreviated title	ISSCC
Country	United States
City	San Francisco
Period	8/02/09 → 12/02/09

Keywords

reference circuits
EWI-15221
Silicon on Insulator
METIS-263776
IR-65428
MOSFET
nano electronics

Access to Document

10.1109/ISSCC.2009.4977443

Annema_A_sub-1V_Bandgap_Voltage_Reference_in_32nm_FinFET_Technology
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Cite this

@inproceedings{7dea105df9584caaaf54dc339074eed7,

title = "A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology",

abstract = "The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.",

keywords = "reference circuits, EWI-15221, Silicon on Insulator, METIS-263776, IR-65428, MOSFET, nano electronics",

author = "Annema, {Anne J.} and P. Veldhorst and G Doornbos and Bram Nauta",

year = "2009",

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day = "8",

doi = "10.1109/ISSCC.2009.4977443",

language = "English",

isbn = "978-1-4244-3458-9",

pages = "332--333",

booktitle = "IEEE International Solid-State Circuits Conference",

publisher = "IEEE Computer Society Press",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2009, ISSCC ; Conference date: 08-02-2009 Through 12-02-2009",

}

Annema, AJ, Veldhorst, P, Doornbos, G & Nauta, B 2009, A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology. in IEEE International Solid-State Circuits Conference. IEEE Computer Society Press, Piscataway, pp. 332-333, IEEE International Solid-State Circuits Conference, ISSCC 2009, San Francisco, United States, 8/02/09. https://doi.org/10.1109/ISSCC.2009.4977443

TY - GEN

T1 - A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

AU - Annema, Anne J.

AU - Veldhorst, P.

AU - Doornbos, G

AU - Nauta, Bram

PY - 2009/2/8

Y1 - 2009/2/8

N2 - The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.

AB - The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.

KW - reference circuits

KW - EWI-15221

KW - Silicon on Insulator

KW - METIS-263776

KW - IR-65428

KW - MOSFET

KW - nano electronics

U2 - 10.1109/ISSCC.2009.4977443

DO - 10.1109/ISSCC.2009.4977443

M3 - Conference contribution

SN - 978-1-4244-3458-9

SP - 332

EP - 333

BT - IEEE International Solid-State Circuits Conference

PB - IEEE Computer Society Press

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2009

Y2 - 8 February 2009 through 12 February 2009

ER -