A sub-mW all-passive RF front end with implicit capacitive stacking achieving 13 dB gain, 5 dB NF and +25 dBm OOB-IIP3

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

Abstract—This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF frontend. A prototype is fabricated in GF22nm FDSOI technology. Operating at fLO= 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25=+66dBm Out-of-band IIP3/IIP2 at 160MHz offset while consuming only 600 _W of power from a 0.8V supply.
Original languageEnglish
Title of host publicationIEEE Radio Frequency Integrated Circuits Symposium 2019
Place of PublicationBoston, Massachusetts, US
PublisherIEEE
Pages91-94
Number of pages4
ISBN (Electronic)978-1-7281-1701-0
DOIs
Publication statusPublished - 3 Jun 2019
EventIEEE Radio Frequency Integrated Circuits Symposium 2019 - Boston Convention and Exhibition Center, Boston, United States
Duration: 2 Jun 20194 Jun 2019

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium 2019
Abbreviated titleRFIC 2019
CountryUnited States
CityBoston
Period2/06/194/06/19

Fingerprint

Noise figure
Electric potential
Switched filters
Capacitors
Mixer circuits
Clocks
Electric power utilization
Switches
Networks (circuits)

Keywords

  • passive mixer
  • N-path filter
  • mixer-first receiver
  • bottom plate mixing
  • capacitive stacking
  • high linearity
  • Low Power
  • RF front-ends

Cite this

Purushothaman, Vijaya Kumar ; Klumperink, Eric A.M. ; Trullas Clavere, Berta ; Nauta, Bram . / A sub-mW all-passive RF front end with implicit capacitive stacking achieving 13 dB gain, 5 dB NF and +25 dBm OOB-IIP3. IEEE Radio Frequency Integrated Circuits Symposium 2019. Boston, Massachusetts, US : IEEE, 2019. pp. 91-94
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title = "A sub-mW all-passive RF front end with implicit capacitive stacking achieving 13 dB gain, 5 dB NF and +25 dBm OOB-IIP3",
abstract = "Abstract—This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF frontend. A prototype is fabricated in GF22nm FDSOI technology. Operating at fLO= 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25=+66dBm Out-of-band IIP3/IIP2 at 160MHz offset while consuming only 600 _W of power from a 0.8V supply.",
keywords = "passive mixer, N-path filter, mixer-first receiver, bottom plate mixing, capacitive stacking, high linearity, Low Power, RF front-ends",
author = "Purushothaman, {Vijaya Kumar} and Klumperink, {Eric A.M.} and {Trullas Clavere}, Berta and Bram Nauta",
year = "2019",
month = "6",
day = "3",
doi = "10.1109/RFIC.2019.8701860",
language = "English",
pages = "91--94",
booktitle = "IEEE Radio Frequency Integrated Circuits Symposium 2019",
publisher = "IEEE",
address = "United States",

}

Purushothaman, VK, Klumperink, EAM, Trullas Clavere, B & Nauta, B 2019, A sub-mW all-passive RF front end with implicit capacitive stacking achieving 13 dB gain, 5 dB NF and +25 dBm OOB-IIP3. in IEEE Radio Frequency Integrated Circuits Symposium 2019. IEEE, Boston, Massachusetts, US, pp. 91-94, IEEE Radio Frequency Integrated Circuits Symposium 2019, Boston, United States, 2/06/19. https://doi.org/10.1109/RFIC.2019.8701860

A sub-mW all-passive RF front end with implicit capacitive stacking achieving 13 dB gain, 5 dB NF and +25 dBm OOB-IIP3. / Purushothaman, Vijaya Kumar; Klumperink, Eric A.M.; Trullas Clavere, Berta; Nauta, Bram .

IEEE Radio Frequency Integrated Circuits Symposium 2019. Boston, Massachusetts, US : IEEE, 2019. p. 91-94.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - Abstract—This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF frontend. A prototype is fabricated in GF22nm FDSOI technology. Operating at fLO= 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25=+66dBm Out-of-band IIP3/IIP2 at 160MHz offset while consuming only 600 _W of power from a 0.8V supply.

AB - Abstract—This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF frontend. A prototype is fabricated in GF22nm FDSOI technology. Operating at fLO= 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25=+66dBm Out-of-band IIP3/IIP2 at 160MHz offset while consuming only 600 _W of power from a 0.8V supply.

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