This paper proposes a discrete-time mixer: the sampled RF input is multiplied by digital sinewave-LO samples. The multiplication is implemented by charge sharing between a unary weighted sampling capacitor and an output capacitor. Spurious responses as low as -56dBc are achieved due to the good linearity and matching properties of capacitors. Four 5GS/s time-interleaved samplers are implemented to cover the entire RF range from 0.1GHz to 4.9GHz, while simultaneously providing 50Ω impedance matching. Any radio channel narrower than 20MHz in this RF range can be received at a fixed 20GS/s sample rate. The worst case spurious response, caused by time-errors in the interleaving clock phases, is at -36dBc (uncalibrated). Other measured parameters, of the 28nm CMOS IC occupying an active area of 0.45mm², over the RF band from 1.1 to 4.9GHz are: NF=14dB-16dB (single-side band), IIP3>+12dBm, P1dB>+2dBm, and P=135mW at a fixed RF sample rate of 20GS/s.
- Radio frequency
- Table lookup
- Frequency modulation
van Manen, L., Klumperink, E. A. M., Cornelissens, K., Borremans, M., & Nauta, B. (2019). A Switched Capacitor Digital SineWave Mixer for Software Defined Radio. IEEE Solid State Circuits Letters, 2(2), 13-16. https://doi.org/10.1109/LSSC.2019.2914859