A syntax based VHDL translation model for high-level synthesis

G.E. Mekenkamp

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publication4th. Belsign workshop
    Place of PublicationSantander, Spain
    Pages-
    Number of pages2
    Publication statusPublished - 30 Oct 1996

    Keywords

    • METIS-119449

    Cite this