A system-level design method for cognitive radio on a reconfigurable multi-processor architecture

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    Abstract

    The future trend of software defined radio (SDR) platforms moves toward reconfigurable Multiprocessor System-on−Chips (MPSoCs). However, there is a gap between the modelling of the dynamic radio applications and the optimized implementation of the application on reconfigurable multiprocessor architectures. We aim to close this gap by applying a system level design method for the modelling and implementation of the dynamic applications on an MPSoC. The state−of−the−art radio technology based on SDR, Cognitive Radio, is considered as a design case to demonstrate the effectiveness of this method.
    Original languageUndefined
    Title of host publicationIEEE International Symposium on System-on-Chip 2007
    Place of PublicationTampere, Finland
    PublisherIEEE Circuits and Systems Society
    Pages3-6
    Number of pages4
    ISBN (Print)1-4244-1368-0
    DOIs
    Publication statusPublished - 20 Nov 2007

    Publication series

    Name
    PublisherIEEE Circuits and Systems Society
    NumberFS-07-05

    Keywords

    • EWI-11410
    • METIS-245780
    • IR-64465

    Cite this

    Zhang, Q., Kokkeler, A. B. J., & Smit, G. J. M. (2007). A system-level design method for cognitive radio on a reconfigurable multi-processor architecture. In IEEE International Symposium on System-on-Chip 2007 (pp. 3-6). [10.1109/ISSOC.2007.4427419] Tampere, Finland: IEEE Circuits and Systems Society. https://doi.org/10.1109/ISSOC.2007.4427419