A system-level design method for cognitive radio on a reconfigurable multi-processor architecture

Q. Zhang; Andre B.J. Kokkeler; Gerardus Johannes Maria Smit

doi:10.1109/ISSOC.2007.4427419

A system-level design method for cognitive radio on a reconfigurable multi-processor architecture

Q. Zhang, Andre B.J. Kokkeler, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

123 Downloads (Pure)

Abstract

The future trend of software defined radio (SDR) platforms moves toward reconfigurable Multiprocessor System-on−Chips (MPSoCs). However, there is a gap between the modelling of the dynamic radio applications and the optimized implementation of the application on reconfigurable multiprocessor architectures. We aim to close this gap by applying a system level design method for the modelling and implementation of the dynamic applications on an MPSoC. The state−of−the−art radio technology based on SDR, Cognitive Radio, is considered as a design case to demonstrate the effectiveness of this method.

Original language	Undefined
Title of host publication	IEEE International Symposium on System-on-Chip 2007
Place of Publication	Tampere, Finland
Publisher	IEEE Circuits and Systems Society
Pages	3-6
Number of pages	4
ISBN (Print)	1-4244-1368-0
DOIs	https://doi.org/10.1109/ISSOC.2007.4427419
Publication status	Published - 20 Nov 2007
Event	IEEE International Symposium on System-on-Chip 2007 - Tampere, Finland Duration: 19 Nov 2007 → 21 Nov 2007

Publication series

Name
Publisher	IEEE Circuits and Systems Society
Number	FS-07-05

Conference

Conference	IEEE International Symposium on System-on-Chip 2007
Period	19/11/07 → 21/11/07
Other	19-21 Nov 2007

Keywords

EWI-11410
METIS-245780
IR-64465

Access to Document

10.1109/ISSOC.2007.4427419

Cite this

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title = "A system-level design method for cognitive radio on a reconfigurable multi-processor architecture",

abstract = "The future trend of software defined radio (SDR) platforms moves toward reconfigurable Multiprocessor System-on−Chips (MPSoCs). However, there is a gap between the modelling of the dynamic radio applications and the optimized implementation of the application on reconfigurable multiprocessor architectures. We aim to close this gap by applying a system level design method for the modelling and implementation of the dynamic applications on an MPSoC. The state−of−the−art radio technology based on SDR, Cognitive Radio, is considered as a design case to demonstrate the effectiveness of this method.",

keywords = "EWI-11410, METIS-245780, IR-64465",

author = "Q. Zhang and Kokkeler, {Andre B.J.} and Smit, {Gerardus Johannes Maria}",

note = "IEEE Catalog Number: 07EX1846C; null ; Conference date: 19-11-2007 Through 21-11-2007",

year = "2007",

month = nov,

day = "20",

doi = "10.1109/ISSOC.2007.4427419",

language = "Undefined",

isbn = "1-4244-1368-0",

publisher = "IEEE Circuits and Systems Society",

number = "FS-07-05",

pages = "3--6",

booktitle = "IEEE International Symposium on System-on-Chip 2007",

address = "United States",

}

Zhang, Q, Kokkeler, ABJ & Smit, GJM 2007, A system-level design method for cognitive radio on a reconfigurable multi-processor architecture. in IEEE International Symposium on System-on-Chip 2007., 10.1109/ISSOC.2007.4427419, IEEE Circuits and Systems Society, Tampere, Finland, pp. 3-6, IEEE International Symposium on System-on-Chip 2007, 19/11/07. https://doi.org/10.1109/ISSOC.2007.4427419

A system-level design method for cognitive radio on a reconfigurable multi-processor architecture. / Zhang, Q.; Kokkeler, Andre B.J.; Smit, Gerardus Johannes Maria.

IEEE International Symposium on System-on-Chip 2007. Tampere, Finland : IEEE Circuits and Systems Society, 2007. p. 3-6 10.1109/ISSOC.2007.4427419.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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