A Technique for Accelerating Injection of Transient Faults in Complex SoCs

A. Rohani, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    9 Citations (Scopus)


    This paper presents a technique for reducing CPU time to perform simulation-based fault-injection experiments in complex SoCs. This technique is fully compatible with commercial HDL simulators with no requirement to develop dedicated compilers. This approach can be easily applied to complex SoC moels, as it is not required to modify the top-level modules of design, moreover, it can inject a wide range of fault models in the design and finally it can achieve a competitive reduction in terms of CPU time compared with other time-accelerated simulation-based approaches. These goals are achieved by using simulator-commands along with partial code modification techniques. The experimental results show that the proposed technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with time-accelerating simulation-based techniques.
    Original languageUndefined
    Title of host publication14th Euromicro Conference on Digital System Design, DSD 2011
    Place of PublicationUSA
    PublisherIEEE Computer Society
    Number of pages8
    ISBN (Print)978-1-4577-1048-3
    Publication statusPublished - 31 Aug 2011
    Event14th EUROMICRO Conference on Digital System Design, DSD 2011 - Oulu, Finland
    Duration: 31 Aug 20112 Sep 2011
    Conference number: 14

    Publication series

    PublisherIEEE Computer Society


    Conference14th EUROMICRO Conference on Digital System Design, DSD 2011
    Abbreviated titleDSD
    Internet address


    • METIS-278872
    • EWI-20681
    • IR-78284

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