A Technique for Accelerating Injection of Transient Faults in Complex SoCs

This paper presents a technique for reducing CPU time to perform simulation-based fault-injection experiments in complex SoCs. This technique is fully compatible with commercial HDL simulators with no requirement to develop dedicated compilers. This approach can be easily applied to complex SoC moels, as it is not required to modify the top-level modules of design, moreover, it can inject a wide range of fault models in the design and finally it can achieve a competitive reduction in terms of CPU time compared with other time-accelerated simulation-based approaches. These goals are achieved by using simulator-commands along with partial code modification techniques. The experimental results show that the proposed technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with time-accelerating simulation-based techniques.