A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

S.M. Louwsma, Adrianus Johannes Maria van Tuijl, M. Vertregt, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    29 Downloads (Pure)

    Abstract

    Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.
    Original languageEnglish
    Title of host publication2007 IEEE Custom Integrated Circuits Conference
    Place of PublicationPiscataway
    PublisherIEEE Computer Society Press
    Pages329-332
    Number of pages4
    ISBN (Print)978-1-4244-1623-3
    DOIs
    Publication statusPublished - 16 Sep 2007
    EventCustom Integrated Circuits Conference, CICC 2007 - San Jose, United States
    Duration: 16 Sep 200719 Sep 2007

    Conference

    ConferenceCustom Integrated Circuits Conference, CICC 2007
    Abbreviated titleCICC 2007
    CountryUnited States
    CitySan Jose
    Period16/09/0719/09/07

    Keywords

    • EWI-10883
    • IR-64288
    • METIS-245726

    Fingerprint Dive into the research topics of 'A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR'. Together they form a unique fingerprint.

    Cite this