A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

S.M. Louwsma; Adrianus Johannes Maria van Tuijl; M. Vertregt; Bram Nauta

doi:10.1109/CICC.2007.4405745

A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

S.M. Louwsma
, Adrianus Johannes Maria van Tuijl
, M. Vertregt
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

399 Downloads (Pure)

Abstract

Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.

Original language	English
Title of host publication	2007 IEEE Custom Integrated Circuits Conference
Place of Publication	Piscataway
Publisher	IEEE
Pages	329-332
Number of pages	4
ISBN (Print)	978-1-4244-1623-3
DOIs	https://doi.org/10.1109/CICC.2007.4405745
Publication status	Published - 16 Sept 2007
Event	Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: 16 Sept 2007 → 19 Sept 2007

Conference

Conference	Custom Integrated Circuits Conference, CICC 2007
Abbreviated title	CICC 2007
Country/Territory	United States
City	San Jose
Period	16/09/07 → 19/09/07

Keywords

EWI-10883
IR-64288
METIS-245726

Access to Document

10.1109/CICC.2007.4405745

Louwsma_CICC2007Accepted author version, 814 KB

Cite this

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title = "A Time-Interleaved Track \& Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR",

abstract = "Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.",

keywords = "EWI-10883, IR-64288, METIS-245726",

author = "S.M. Louwsma and \{van Tuijl\}, \{Adrianus Johannes Maria\} and M. Vertregt and Bram Nauta",

year = "2007",

month = sep,

day = "16",

doi = "10.1109/CICC.2007.4405745",

language = "English",

isbn = "978-1-4244-1623-3",

pages = "329--332",

booktitle = "2007 IEEE Custom Integrated Circuits Conference",

publisher = "IEEE",

address = "United States",

note = "Custom Integrated Circuits Conference, CICC 2007, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",

}

Louwsma, SM, van Tuijl, AJM, Vertregt, M & Nauta, B 2007, A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR. in 2007 IEEE Custom Integrated Circuits Conference. IEEE, Piscataway, pp. 329-332, Custom Integrated Circuits Conference, CICC 2007, San Jose, California, United States, 16/09/07. https://doi.org/10.1109/CICC.2007.4405745

TY - GEN

T1 - A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

AU - Louwsma, S.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Vertregt, M.

AU - Nauta, Bram

PY - 2007/9/16

Y1 - 2007/9/16

N2 - Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.

AB - Abstract—A 16-channel time-interleaved Track and Hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.

KW - EWI-10883

KW - IR-64288

KW - METIS-245726

U2 - 10.1109/CICC.2007.4405745

DO - 10.1109/CICC.2007.4405745

M3 - Conference contribution

SN - 978-1-4244-1623-3

SP - 329

EP - 332

BT - 2007 IEEE Custom Integrated Circuits Conference

PB - IEEE

CY - Piscataway

T2 - Custom Integrated Circuits Conference, CICC 2007

Y2 - 16 September 2007 through 19 September 2007

ER -

A Time-Interleaved Track & Hold in 0.13μm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR

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Keywords

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