Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper we show how a special form of equalization, pulse-width pre-emphasis, can significantly increase the data rate for a given length of uninterrupted interconnect, especially if used in combination with lowohmic termination and twisted differential interconnects. To validate these techniques, a bus-transceiver test chip in a 0.13μm, 1.2V, 6M copper CMOS process has been designed. The chip uses 10mm long differential interconnects with wire widths and spacing of only 0.4μm. With transceivers operating in conventional mode, the chip achieves only 0.55Gb/s/ch. The achievable data rate increases to 3Gb/s/ch (consuming 2pJ/bit) if pulse-width pre-emphasis and low-ohmic termination are turned on.
|Title of host publication||16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005|
|Place of Publication||Utrecht|
|Number of pages||5|
|Publication status||Published - Nov 2005|
|Event||16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005 - Veldhoven, Netherlands|
Duration: 17 Nov 2005 → 18 Nov 2005
Conference number: 16
|Workshop||16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005|
|Period||17/11/05 → 18/11/05|
- Data bus
- On-chip dommunication
- Intersymbol interference (ISI)
Schinkel, D., Mensink, E., Klumperink, E., van Tuijl, E., & Nauta, B. (2005). A Transceiver for High-Speed Global On-Chip Data Communication. In 16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005 (pp. 279-283). Utrecht: STW.