A two step hardware design method using CλaSH

Rinse Wester, C.P.R. Baaij, Jan Kuper

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 6 Citations

Abstract

In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the CλaSH HDL, offer adequate abstraction mechanisms such as polymorphism and higher-order functions. This paper describes a two step design method to implement a DSP application on an FPGA, starting from a mathematical specification, followed by an implementation in CλaSH. A non trivial application, a particle filter, is used to evaluate both the method and CλaSH. First, a straightforward translation is performed from the mathematical definition of a particle filtering to Haskell, a functional programming language with syntax and semantics similar to CλaSH. Secondly, minor changes are applied to the Haskell implementation so that it is accepted by the CλaSH compiler. The resulting hardware produced by our method is evaluated and shows that this method eases reasoning about structure and parallelism in both the mathematical definition and the resulting hardware.
LanguageUndefined
Title of host publication22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Place of PublicationUSA
PublisherIEEE Computer Society
Pages181-188
Number of pages8
ISBN (Print)978-1-4673-2257-7
DOIs
Publication statusPublished - 29 Aug 2012
Event22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
Duration: 29 Aug 201231 Aug 2012
Conference number: 22
http://www.fpl2012.org/

Publication series

Name
PublisherIEEE Computer Society

Conference

Conference22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Abbreviated titleFPL
CountryNorway
CityOslo
Period29/08/1231/08/12
Internet address

Keywords

  • EWI-22585
  • EC Grant Agreement nr.: FP7/248465
  • Design method
  • METIS-289799
  • Particle filter
  • IR-82306
  • CλaSH
  • FPGA

Cite this

Wester, R., Baaij, C. P. R., & Kuper, J. (2012). A two step hardware design method using CλaSH. In 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 181-188). USA: IEEE Computer Society. https://doi.org/10.1109/FPL.2012.6339258
Wester, Rinse ; Baaij, C.P.R. ; Kuper, Jan. / A two step hardware design method using CλaSH. 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. USA : IEEE Computer Society, 2012. pp. 181-188
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Wester, R, Baaij, CPR & Kuper, J 2012, A two step hardware design method using CλaSH. in 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. IEEE Computer Society, USA, pp. 181-188, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 29/08/12. https://doi.org/10.1109/FPL.2012.6339258

A two step hardware design method using CλaSH. / Wester, Rinse; Baaij, C.P.R.; Kuper, Jan.

22nd International Conference on Field Programmable Logic and Applications, FPL 2012. USA : IEEE Computer Society, 2012. p. 181-188.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Wester R, Baaij CPR, Kuper J. A two step hardware design method using CλaSH. In 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. USA: IEEE Computer Society. 2012. p. 181-188 https://doi.org/10.1109/FPL.2012.6339258