Abstract
| Original language | Undefined |
|---|---|
| Title of host publication | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 |
| Place of Publication | USA |
| Publisher | IEEE Computer Society |
| Pages | 181-188 |
| Number of pages | 8 |
| ISBN (Print) | 978-1-4673-2257-7 |
| DOIs | |
| Publication status | Published - 29 Aug 2012 |
| Event | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway Duration: 29 Aug 2012 → 31 Aug 2012 Conference number: 22 http://www.fpl2012.org/ |
Publication series
| Name | |
|---|---|
| Publisher | IEEE Computer Society |
Conference
| Conference | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 |
|---|---|
| Abbreviated title | FPL |
| Country | Norway |
| City | Oslo |
| Period | 29/08/12 → 31/08/12 |
| Internet address |
Keywords
- EWI-22585
- EC Grant Agreement nr.: FP7/248465
- Design method
- METIS-289799
- Particle filter
- IR-82306
- CλaSH
- FPGA
Cite this
}
A two step hardware design method using CλaSH. / Wester, Rinse; Baaij, C.P.R.; Kuper, Jan.
22nd International Conference on Field Programmable Logic and Applications, FPL 2012. USA : IEEE Computer Society, 2012. p. 181-188.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A two step hardware design method using CλaSH
AU - Wester, Rinse
AU - Baaij, C.P.R.
AU - Kuper, Jan
N1 - eemcs-eprint-22585
PY - 2012/8/29
Y1 - 2012/8/29
N2 - In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the CλaSH HDL, offer adequate abstraction mechanisms such as polymorphism and higher-order functions. This paper describes a two step design method to implement a DSP application on an FPGA, starting from a mathematical specification, followed by an implementation in CλaSH. A non trivial application, a particle filter, is used to evaluate both the method and CλaSH. First, a straightforward translation is performed from the mathematical definition of a particle filtering to Haskell, a functional programming language with syntax and semantics similar to CλaSH. Secondly, minor changes are applied to the Haskell implementation so that it is accepted by the CλaSH compiler. The resulting hardware produced by our method is evaluated and shows that this method eases reasoning about structure and parallelism in both the mathematical definition and the resulting hardware.
AB - In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the CλaSH HDL, offer adequate abstraction mechanisms such as polymorphism and higher-order functions. This paper describes a two step design method to implement a DSP application on an FPGA, starting from a mathematical specification, followed by an implementation in CλaSH. A non trivial application, a particle filter, is used to evaluate both the method and CλaSH. First, a straightforward translation is performed from the mathematical definition of a particle filtering to Haskell, a functional programming language with syntax and semantics similar to CλaSH. Secondly, minor changes are applied to the Haskell implementation so that it is accepted by the CλaSH compiler. The resulting hardware produced by our method is evaluated and shows that this method eases reasoning about structure and parallelism in both the mathematical definition and the resulting hardware.
KW - EWI-22585
KW - EC Grant Agreement nr.: FP7/248465
KW - Design method
KW - METIS-289799
KW - Particle filter
KW - IR-82306
KW - CλaSH
KW - FPGA
U2 - 10.1109/FPL.2012.6339258
DO - 10.1109/FPL.2012.6339258
M3 - Conference contribution
SN - 978-1-4673-2257-7
SP - 181
EP - 188
BT - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
PB - IEEE Computer Society
CY - USA
ER -