TY - GEN
T1 - A versatile UDP/IP based PC ↔ FPGA communication platform
AU - Alachiotis, Nikolaos
AU - Berger, Simon A.
AU - Stamatakis, Alexandros
PY - 2012
Y1 - 2012
N2 - We present a substantially improved version of our popular UDP/IP core for simple and fast PC ↔ FPGA communication over Gigabit Ethernet. We provide a novel feature to automatically configure (previously hard-coded) internal settings on the FPGA. Thereby, we substantially reduce the installation overhead when a FPGA shall communicate with several different PCs. The UDP/IP core is designed to occupy a minimum amount of hardware resources on the FPGA. On the PC side, this new automatic configuration protocol can be used and invoked via a C software interface which provides convenient functions for setting up the connection to the FPGA device and sending/retrieving arrays of common C data types to/from the UDP/IP core on the FPGA. The initial UDP/IP core version is available under the LGPL license at http://opencores.org/project, udp-ip-core while the improved version of the core, including the C software interface (also under LGPL), is available at http://opencores.org/project, pc-fpga-com.
AB - We present a substantially improved version of our popular UDP/IP core for simple and fast PC ↔ FPGA communication over Gigabit Ethernet. We provide a novel feature to automatically configure (previously hard-coded) internal settings on the FPGA. Thereby, we substantially reduce the installation overhead when a FPGA shall communicate with several different PCs. The UDP/IP core is designed to occupy a minimum amount of hardware resources on the FPGA. On the PC side, this new automatic configuration protocol can be used and invoked via a C software interface which provides convenient functions for setting up the connection to the FPGA device and sending/retrieving arrays of common C data types to/from the UDP/IP core on the FPGA. The initial UDP/IP core version is available under the LGPL license at http://opencores.org/project, udp-ip-core while the improved version of the core, including the C software interface (also under LGPL), is available at http://opencores.org/project, pc-fpga-com.
KW - FPGA
KW - PC-FPGA communication
KW - UDP/IP
UR - http://www.scopus.com/inward/record.url?scp=84874182290&partnerID=8YFLogxK
U2 - 10.1109/ReConFig.2012.6416725
DO - 10.1109/ReConFig.2012.6416725
M3 - Conference contribution
AN - SCOPUS:84874182290
SN - 978-1-4673-2919-4
T3 - International Conference on Reconfigurable Computing and FPGAs )ReConFig)
BT - 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
PB - IEEE
CY - Piscataway, NJ
T2 - 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
Y2 - 5 December 2012 through 7 December 2012
ER -