A virtual channel router for on-chip networks

N.K. Kavaldjiev, G.J.M. Smit, P.G. Jansen

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    Abstract

    This paper proposes an architecture of a virtual channel router for an on-chip network1. The router has simple dynamic arbitration which is deterministic and fair. We show that the size of the proposed router is reduced by 49% and the speed increases 1.4 times compared to a conventional virtual channel router.
    Original languageEnglish
    Title of host publicationIEEE International SOC Conference, 2004
    Subtitle of host publicationProceedings
    EditorsJohn Chickanosky, Dong Ha, Richard Auletta
    Place of PublicationLos Alamitos, CA
    PublisherIEEE Computer Society
    Pages289-293
    Number of pages5
    ISBN (Print)0-7803-8445-8
    DOIs
    Publication statusPublished - Sep 2004
    EventIEEE International Systems-on-Chip Conference, SOC 2004 - Hilton Santa Clara, Santa Clara, United States
    Duration: 12 Sep 200415 Sep 2004

    Conference

    ConferenceIEEE International Systems-on-Chip Conference, SOC 2004
    Abbreviated titleSOC
    CountryUnited States
    CitySanta Clara
    Period12/09/0415/09/04

    Keywords

    • CAES-EEA: Efficient Embedded Architectures

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