Abstract
This paper proposes an architecture of a virtual channel router for an on-chip network1. The router has simple dynamic arbitration which is deterministic and fair. We show that the size of the proposed router is reduced by 49% and the speed increases 1.4 times compared to a conventional virtual channel router.
Original language | English |
---|---|
Title of host publication | IEEE International SOC Conference, 2004 |
Subtitle of host publication | Proceedings |
Editors | John Chickanosky, Dong Ha, Richard Auletta |
Place of Publication | Los Alamitos, CA |
Publisher | IEEE |
Pages | 289-293 |
Number of pages | 5 |
ISBN (Print) | 0-7803-8445-8 |
DOIs | |
Publication status | Published - Sept 2004 |
Event | IEEE International Systems-on-Chip Conference, SOC 2004 - Hilton Santa Clara, Santa Clara, United States Duration: 12 Sept 2004 → 15 Sept 2004 |
Conference
Conference | IEEE International Systems-on-Chip Conference, SOC 2004 |
---|---|
Abbreviated title | SOC |
Country/Territory | United States |
City | Santa Clara |
Period | 12/09/04 → 15/09/04 |
Keywords
- CAES-EEA: Efficient Embedded Architectures