A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

Darwei Ye, Ping Lu, Pietro Andreani, Ronan van der Zee

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    92 Downloads (Pure)

    Abstract

    This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.
    Original languageEnglish
    Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2013
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages169-172
    Number of pages4
    ISBN (Electronic)978-1-4673-5762-39, 978-1-4673-5761-6
    ISBN (Print)978-1-4673-5760-9
    DOIs
    Publication statusPublished - 19 May 2013
    EventIEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijng, China
    Duration: 19 May 201323 May 2013

    Publication series

    NameProceedings IEEE International Symposium on Circuits and Systems (ISCAS)
    PublisherIEEE Press
    Volume2013
    ISSN (Print)0271-4302
    ISSN (Electronic)2158-1525

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2013
    Abbreviated titleISCAS
    CountryChina
    CityBeijng
    Period19/05/1323/05/13

    Keywords

    • EWI-23824
    • IR-87489
    • METIS-300076

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