A wide bandwidth fractional-N synthesizer for LTE
with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

Darwei Ye; Ping Lu; Pietro Andreani; Ronan van der Zee

doi:10.1109/ISCAS.2013.6571809

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

Darwei Ye, Ping Lu, Pietro Andreani, Ronan van der Zee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

279 Downloads (Pure)

Abstract

This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2013
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	169-172
Number of pages	4
ISBN (Electronic)	978-1-4673-5762-39, 978-1-4673-5761-6
ISBN (Print)	978-1-4673-5760-9
DOIs	https://doi.org/10.1109/ISCAS.2013.6571809
Publication status	Published - 19 May 2013
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijng, China Duration: 19 May 2013 → 23 May 2013

Publication series

Name	Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE Press
Volume	2013
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2013
Abbreviated title	ISCAS
Country/Territory	China
City	Beijng
Period	19/05/13 → 23/05/13

Keywords

EWI-23824
IR-87489
METIS-300076

Access to Document

10.1109/ISCAS.2013.6571809

Ye2013wideAccepted author version, 372 KB

Cite this

Ye, D., Lu, P., Andreani, P., & van der Zee, R. (2013). A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. In IEEE International Symposium on Circuits and Systems, ISCAS 2013 (pp. 169-172). (Proceedings IEEE International Symposium on Circuits and Systems (ISCAS); Vol. 2013). IEEE. https://doi.org/10.1109/ISCAS.2013.6571809

@inproceedings{dbf5083d05c443cab8c80850c6851265,

title = "A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing",

abstract = "This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.",

keywords = "EWI-23824, IR-87489, METIS-300076",

author = "Darwei Ye and Ping Lu and Pietro Andreani and {van der Zee}, Ronan",

year = "2013",

month = may,

day = "19",

doi = "10.1109/ISCAS.2013.6571809",

language = "English",

isbn = "978-1-4673-5760-9",

series = "Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE",

pages = "169--172",

booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2013",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2013, ISCAS ; Conference date: 19-05-2013 Through 23-05-2013",

}

Ye, D, Lu, P, Andreani, P & van der Zee, R 2013, A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. in IEEE International Symposium on Circuits and Systems, ISCAS 2013. Proceedings IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2013, IEEE, Piscataway, NJ, pp. 169-172, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijng, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6571809

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. / Ye, Darwei; Lu, Ping; Andreani, Pietro et al.
IEEE International Symposium on Circuits and Systems, ISCAS 2013. Piscataway, NJ: IEEE, 2013. p. 169-172 (Proceedings IEEE International Symposium on Circuits and Systems (ISCAS); Vol. 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

AU - Ye, Darwei

AU - Lu, Ping

AU - Andreani, Pietro

AU - van der Zee, Ronan

PY - 2013/5/19

Y1 - 2013/5/19

N2 - This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.

AB - This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.

KW - EWI-23824

KW - IR-87489

KW - METIS-300076

U2 - 10.1109/ISCAS.2013.6571809

DO - 10.1109/ISCAS.2013.6571809

M3 - Conference contribution

SN - 978-1-4673-5760-9

T3 - Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)

SP - 169

EP - 172

BT - IEEE International Symposium on Circuits and Systems, ISCAS 2013

PB - IEEE

CY - Piscataway, NJ

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2013

Y2 - 19 May 2013 through 23 May 2013

ER -

Ye D, Lu P, Andreani P, van der Zee R. A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. In IEEE International Symposium on Circuits and Systems, ISCAS 2013. Piscataway, NJ: IEEE. 2013. p. 169-172. (Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)). doi: 10.1109/ISCAS.2013.6571809