This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 21mA from a 1 V supply.
|Name||Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)|
|Conference||IEEE International Symposium on Circuits and Systems, ISCAS 2013|
|Period||19/05/13 → 23/05/13|