Accelerated Phylogenetics on the AMD Versal Adaptive SoC

Phylogenetics study the evolutionary history of organisms using an iterative procedure of creating and evaluating phylogenetic trees. This procedure is highly compute-intensive; constructing a large phylogenetic tree requires hundreds to thousands of CPU hours. Most phylogenetic analyses today rely either on Maximum Likelihood (ML) or Bayesian Inference (BI) methods for inferring phylogenetic trees; the Phylogenetic Likelihood Function (PLF) is employed in both ML and BI approaches as the tree-evaluation function, accounting for up to 95% of the overall analysis time. In this work, we explore the AMD Versal Adaptive SoC architecture for accelerating the PLF that heavily relies on matrix multiplication operations. We find that the tight integration of domain-specific processors (AI Engines) with Programmable Logic (PL) in the Versal architecture is highly suitable for the needs of the PLF: we map the core operation of the PLF (matrix multiplication) to the AI Engines and deploy special-purpose units in the PL for PLF-specific data caching and input/output management, as well as numerical scaling that is a prerequisite for yielding numerically stable solutions for large-scale phylogenetic studies. We conducted a thorough performance analysis to leverage the platform capabilities to guide matrix-multiplication acceleration that requires close PL-AIE cooperation. We observed between and higher computational power of the Versal SoC than one x86 CPU core (both AMD and Intel) using AVX2 intrinsics, and between and higher performance than eight cores. For the full system, we observe comparable performance () with eight CPU cores due to device memory access and PCIe limitations, showing the potential of the Versal architecture in accelerating a distinct application from DSP/AI, its primary design focus.