ADC Clock Jitter Requirements for Software Radio Receivers

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)
64 Downloads (Pure)

Abstract

The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.
Original languageEnglish
Title of host publicationIEEE 60th Vehicular Technology Conference, 2004. VTC2004
Place of PublicationUSA, Los Angeles
PublisherIEEE
Pages-
ISBN (Print)0-7803-8522-5
DOIs
Publication statusPublished - 26 Sep 2004
EventIEEE 60th Vehicular Technology Conference 2004. Fall 2004 - Los Angeles, United States
Duration: 26 Sep 200429 Sep 2004
Conference number: 60

Conference

ConferenceIEEE 60th Vehicular Technology Conference 2004. Fall 2004
Abbreviated titleVTC Fall 2004
CountryUnited States
CityLos Angeles
Period26/09/0429/09/04

Fingerprint

Software radio
Radio receivers
Digital to analog conversion
Jitter
Clocks
Sampling
Timing jitter
Phase noise
Power spectrum

Keywords

  • IR-48126
  • METIS-219328

Cite this

Arkesteijn, V. J., Klumperink, E. A. M., & Nauta, B. (2004). ADC Clock Jitter Requirements for Software Radio Receivers. In IEEE 60th Vehicular Technology Conference, 2004. VTC2004 (pp. -). USA, Los Angeles: IEEE. https://doi.org/10.1109/VETECF.2004.1400385
Arkesteijn, V.J. ; Klumperink, Eric A.M. ; Nauta, Bram. / ADC Clock Jitter Requirements for Software Radio Receivers. IEEE 60th Vehicular Technology Conference, 2004. VTC2004. USA, Los Angeles : IEEE, 2004. pp. -
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abstract = "The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.",
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Arkesteijn, VJ, Klumperink, EAM & Nauta, B 2004, ADC Clock Jitter Requirements for Software Radio Receivers. in IEEE 60th Vehicular Technology Conference, 2004. VTC2004. IEEE, USA, Los Angeles, pp. -, IEEE 60th Vehicular Technology Conference 2004. Fall 2004, Los Angeles, United States, 26/09/04. https://doi.org/10.1109/VETECF.2004.1400385

ADC Clock Jitter Requirements for Software Radio Receivers. / Arkesteijn, V.J.; Klumperink, Eric A.M.; Nauta, Bram.

IEEE 60th Vehicular Technology Conference, 2004. VTC2004. USA, Los Angeles : IEEE, 2004. p. -.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.

AB - The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.

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Arkesteijn VJ, Klumperink EAM, Nauta B. ADC Clock Jitter Requirements for Software Radio Receivers. In IEEE 60th Vehicular Technology Conference, 2004. VTC2004. USA, Los Angeles: IEEE. 2004. p. - https://doi.org/10.1109/VETECF.2004.1400385