ADC Clock Jitter Requirements for Software Radio Receivers

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    7 Citations (Scopus)
    99 Downloads (Pure)


    The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.
    Original languageEnglish
    Title of host publicationIEEE 60th Vehicular Technology Conference, 2004. VTC2004
    Place of PublicationUSA, Los Angeles
    ISBN (Print)0-7803-8522-5
    Publication statusPublished - 26 Sep 2004
    EventIEEE 60th Vehicular Technology Conference 2004. Fall 2004 - Los Angeles, United States
    Duration: 26 Sep 200429 Sep 2004
    Conference number: 60


    ConferenceIEEE 60th Vehicular Technology Conference 2004. Fall 2004
    Abbreviated titleVTC Fall 2004
    CountryUnited States
    CityLos Angeles


    • IR-48126
    • METIS-219328


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