The Analogue-to-Digital Converter (ADC) is one of the most typical and widely used mixed-signal circuits. They are applied in video, audio, high-speed communications systems and so on. Many ADCs are integrated into platform-based designs, the architecture which normally contains of standard blocks such as memories, digital processors, RF and analogue front-ends. As testing such a system is a complex task, the related test cost of the platforms is a major part of the overall chip costs. The test cost of ADCs has a relatively high percentage of the total test cost of the chips. The major challenges of the ADC production test cost are the expensive test equipment and the long test times. An architecture of an ADC test infrastructure in a platform-based design has been proposed in our research, which consists of the embedded digital processor(s), the ADC under test, aiding digital test stimuli circuits and memory. The embedded processor can generate the test input signal with the aiding circuits and post-process the output data. The aiding circuits adapt the normal digital signal from the processors to be more suitable for ADC testing. The memory can store the conversion output data. In this thesis, we basically propose three novel methods. The first method is using the adaptive pulse wave to test the dynamic parameters. In this method, a number of pulse waves with different duty cycles are applied to the ADC under test as the test stimulus. As the spectrum of a pulse wave is related to its duty cycle, the spectrum of a sine wave is emulated by the spectrum of a number of pulse waves with different duty cycles. In this way, the dynamic parameters of the ADC under test can be calculated. The results can be used to filter out the faulty devices before the ADC under test proceeds to the conventional production testing. In the second method, only a simple pulse wave is applied as the test stimulus. In the post-processing, an unconventional method has been proposed. Signature results are obtained by comparing the similarity of the output waveforms between the golden devices and the device under test (DUT). The signature results can classify the faulty device and the fault-free devices. As the test stimulus is easy to generate and the post-processing is simple, it is very suitable to apply in a multi-site test environment. The method has been proposed as a quick pre-test to filter out the faulty devices before the conventional production test of DUTs. For the third method, a machine-learning based test method to predict the dynamic parameters of the ADCs has been proposed. A low-quality pulse wave is exploited as the test stimulus. The signature test is carried out by applying the pulse wave input signal. For the training devices, both the signature test and conventional specification tests are carried out. A mapping function can be built up between the signature results and the specification results. For the DUTs, only a signature test is required. Afterwards, the specification results of the DUTs can be predicted by substituting the signature results to the mapping function. As the signature test is simple and suitable for multi-site test, the proposed test method can reduce the test time compared with the conventional test. Summarizing, based on our proposed test infrastructure, either signature results are used to only filter out the faulty devices or accurately predicted dynamic results of the ADCs can be obtained. Both the test input signal generation and post-processing can be carried out on the embedded processor. In this way, it relaxes the requirements of the ATE, which is normally the bottleneck in ADC production testing. It is especially suitable for a multi-site test environment. As result, it can reduce the test time and the cost of ADC production testing.
|Award date||6 Feb 2014|
|Place of Publication||Enschede|
|Publication status||Published - 6 Feb 2014|
- CAES-TDT: Testable Design and Test
- Digital Stimuli
- ADC testing
- Mixed-signal testing