Adding synchronous and LSSD modes to asynchronous circuits

Kees van Berkel, Ad Peeters, F.J. te Beest

    Research output: Contribution to journalArticleAcademicpeer-review

    3 Citations (Scopus)

    Abstract

    A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.
    Original languageUndefined
    Pages (from-to)461-471
    Number of pages11
    JournalMicroprocessors and microsystems
    Volume27
    Issue number9
    DOIs
    Publication statusPublished - 2003

    Keywords

    • Shift register latches
    • Test pattern generation
    • Level-sensitive scan design
    • METIS-215131
    • IR-75026
    • asynchronous circuits

    Cite this