A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.
- Shift register latches
- Test pattern generation
- Level-sensitive scan design
- asynchronous circuits
van Berkel, K., Peeters, A., & te Beest, F. J. (2003). Adding synchronous and LSSD modes to asynchronous circuits. Microprocessors and microsystems, 27(9), 461-471. https://doi.org/10.1016/S0141-9331(03)00095-4