Advanced fabrication of Si nanowire FET structures by means of a parallel approach

J. Li, S. Pud, D. Mayer, S. Vitusevich

Research output: Contribution to journalArticleAcademicpeer-review

12 Citations (Scopus)

Abstract

In this paper we present fabricated Si nanowires (NWs) of different dimensions with enhanced electrical characteristics. The parallel fabrication process is based on nanoimprint lithography using high-quality molds, which facilitates the realization of 50 nm-wide NW field-effect transistors (FETs). The imprint molds were fabricated by using a wet chemical anisotropic etching process. The wet chemical etch results in well-defined vertical sidewalls with edge roughness (3σ) as small as 2 nm, which is about four times better compared with the roughness usually obtained for reactive-ion etching molds. The quality of the mold was studied using atomic force microscopy and scanning electron microscopy image data. The use of the high-quality mold leads to almost 100% yield during fabrication of Si NW FETs as well as to an exceptional quality of the surfaces of the devices produced. To characterize the Si NW FETs, we used noise spectroscopy as a powerful method for evaluating device performance and the reliability of structures with nanoscale dimensions. The Hooge parameter of fabricated FET structures exhibits an average value of 1.6×10-3. This value reflects the high quality of Si NW FETs fabricated by means of a parallel approach that uses a nanoimprint mold and cost-efficient technology.

Original languageEnglish
Article number275302
JournalNanotechnology
Volume25
Issue number27
DOIs
Publication statusPublished - 11 Jul 2014
Externally publishedYes

Keywords

  • Nanoimprint
  • Noise
  • Roughness
  • Silicon nanowires

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