A new front-end has been implemented on a pixel detector readout chip developed in a commercial 0.25?m CMOS technology for the ALICE and LHCb experiments. This technology proves to be radiation tolerant when special layout techniques are used, and provides sufficient density for these applications. A non-standard topology was used for the front-end, to achieve low noise and fast return to zero of the preamplifier to be immune to pile-up of subsequent input signals. The chip is a matrix of 32 columns each containing 256 readout cells. Each readout cell comprises this frontend and digital readout circuitry, and has a static power consumption of about 60 ?W. The complete readout cell will be described, but the paper will be mainly focussed on the front-end section.
|Title of host publication||Sixth Workshop on Electronics for LHC Experiments (LEB2000)|
|Place of Publication||Geneva, Switzerland|
|Number of pages||5|
|Publication status||Published - Sep 2000|