An Array Processor Design Methodology for Real-Time Systems

J.A.K.S. Jayasinghe; F. Moelaert El-Hadidy; O.E. Herrmann

doi:10.1109/ISCAS.1991.176194

An Array Processor Design Methodology for Real-Time Systems

J.A.K.S. Jayasinghe, F. Moelaert El-Hadidy, O.E. Herrmann

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

An array processor design methodology suitable for hard real-time systems is presented. Scheduling and projection of the dependence graph (DG) are solved using integer programming. By exploring the regularity of the DG it is possible to solve the necessary IP problems in an efficient manner. This methodology provides a unified approach for linear and nonlinear projection of regular and partially regular DGs

Original language	English
Title of host publication	1991 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Singapore
Pages	3062-3065
Number of pages	4
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.1991.176194
Publication status	Published - 11 Jun 1991
Event	IEEE International Symposium on Circuits and Systems, ISCAS 1991 - Singapore, Singapore Duration: 11 Jun 1991 → 14 Jun 1991

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 1991
Abbreviated title	ISCAS
Country/Territory	Singapore
City	Singapore
Period	11/06/91 → 14/06/91

Keywords

Scheduling
Real time systems
Parallel architectures

Access to Document

10.1109/ISCAS.1991.176194

Jayasinghe1991arrayFinal published version, 422 KB

1 Conference contribution

An Array Processor Design Methodology for Real-time Systems
Jayasinghe, J. A. K. S., El hadidy, F. & Herrmann, O. E., 3 Apr 1991, Proceedings of the IEEE/ProRISC Symposium on Circuits, Systems and Signal Processing. Veen, J. P. (ed.). Veldhoven, The Netherlands: STW, p. 210-213 4 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Cite this

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title = "An Array Processor Design Methodology for Real-Time Systems",

abstract = "An array processor design methodology suitable for hard real-time systems is presented. Scheduling and projection of the dependence graph (DG) are solved using integer programming. By exploring the regularity of the DG it is possible to solve the necessary IP problems in an efficient manner. This methodology provides a unified approach for linear and nonlinear projection of regular and partially regular DGs",

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Y1 - 1991/6/11

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KW - Scheduling

KW - Real time systems

KW - Parallel architectures

U2 - 10.1109/ISCAS.1991.176194

DO - 10.1109/ISCAS.1991.176194

M3 - Conference contribution

SN - 0-7803-0050-5

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SP - 3062

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T2 - IEEE International Symposium on Circuits and Systems, ISCAS 1991

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ER -

An Array Processor Design Methodology for Real-Time Systems

Abstract

Conference

Keywords

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Research output

An Array Processor Design Methodology for Real-time Systems

Cite this