An audio FIR-DAC in a BCD process for high power Class-D amplifiers

T.S. Doorn, Adrianus Johannes Maria van Tuijl, Daniel Schinkel, Anne J. Annema, M. Berkhout, M. Berkhout, Bram Nauta

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

9 Citations (Scopus)
175 Downloads (Pure)

Abstract

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at Vdd = 5 V and the chip area is 2 mm2 including the reference diode that can be shared by more channels
Original languageEnglish
Title of host publicationthe 31st European Solid-State Circuits Conference (ESSCIRC 2005)
Place of PublicationGrenoble
PublisherIEEE Computer Society
Pages459-462
Number of pages4
ISBN (Print)0780392051
DOIs
Publication statusPublished - Sep 2005
Event31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France
Duration: 12 Sep 200516 Sep 2005
Conference number: 31

Publication series

Name
PublisherIEEE

Conference

Conference31st European Solid-State Circuits Conference, ESSCIRC 2005
Abbreviated titleESSCIRC
CountryFrance
CityGrenoble
Period12/09/0516/09/05

Fingerprint

Pulse width modulation
Impulse response
Diodes
Electric power utilization
Electric potential

Keywords

  • METIS-224244
  • EWI-14516
  • IR-52604

Cite this

Doorn, T. S., van Tuijl, A. J. M., Schinkel, D., Annema, A. J., Berkhout, M., Berkhout, M., & Nauta, B. (2005). An audio FIR-DAC in a BCD process for high power Class-D amplifiers. In the 31st European Solid-State Circuits Conference (ESSCIRC 2005) (pp. 459-462). Grenoble: IEEE Computer Society. https://doi.org/10.1109/ESSCIR.2005.1541659
Doorn, T.S. ; van Tuijl, Adrianus Johannes Maria ; Schinkel, Daniel ; Annema, Anne J. ; Berkhout, M. ; Berkhout, M. ; Nauta, Bram. / An audio FIR-DAC in a BCD process for high power Class-D amplifiers. the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble : IEEE Computer Society, 2005. pp. 459-462
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abstract = "A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at Vdd = 5 V and the chip area is 2 mm2 including the reference diode that can be shared by more channels",
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Doorn, TS, van Tuijl, AJM, Schinkel, D, Annema, AJ, Berkhout, M, Berkhout, M & Nauta, B 2005, An audio FIR-DAC in a BCD process for high power Class-D amplifiers. in the 31st European Solid-State Circuits Conference (ESSCIRC 2005). IEEE Computer Society, Grenoble, pp. 459-462, 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSCIR.2005.1541659

An audio FIR-DAC in a BCD process for high power Class-D amplifiers. / Doorn, T.S.; van Tuijl, Adrianus Johannes Maria; Schinkel, Daniel; Annema, Anne J.; Berkhout, M.; Berkhout, M.; Nauta, Bram.

the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble : IEEE Computer Society, 2005. p. 459-462.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - Schinkel, Daniel

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N2 - A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at Vdd = 5 V and the chip area is 2 mm2 including the reference diode that can be shared by more channels

AB - A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at Vdd = 5 V and the chip area is 2 mm2 including the reference diode that can be shared by more channels

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Doorn TS, van Tuijl AJM, Schinkel D, Annema AJ, Berkhout M, Berkhout M et al. An audio FIR-DAC in a BCD process for high power Class-D amplifiers. In the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble: IEEE Computer Society. 2005. p. 459-462 https://doi.org/10.1109/ESSCIR.2005.1541659