An audio FIR-DAC in a BCD process for high power Class-D amplifiers

T.S. Doorn, E. van Tuijl, D. Schinkel, A.J. Annema, M. Berkhout, B. Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    9 Citations (Scopus)
    353 Downloads (Pure)

    Abstract

    A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at Vdd = 5 V and the chip area is 2 mm2 including the reference diode that can be shared by more channels
    Original languageEnglish
    Title of host publication31st European Solid-State Circuits Conference (ESSCIRC 2005)
    Place of PublicationPiscataway, NJ
    PublisherIEEE Computer Society
    Pages459-462
    Number of pages4
    ISBN (Print)0-7803-9205-1
    DOIs
    Publication statusPublished - Sep 2005
    Event31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France
    Duration: 12 Sep 200516 Sep 2005
    Conference number: 31

    Publication series

    NameProceedings European Solid-State Circuits Conference (ESSCIRC)
    PublisherIEEE
    Volume2005
    ISSN (Print)1930-8833

    Conference

    Conference31st European Solid-State Circuits Conference, ESSCIRC 2005
    Abbreviated titleESSCIRC
    CountryFrance
    CityGrenoble
    Period12/09/0516/09/05

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