An Automated Design-flow for FPGA-based Sequential Simulation

P.T. Wolkotte, J.H. Rutgers, P.K.F. Holzenspies, M. Westmijze, M. Westmijze, R. Blumink, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

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    In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.
    Original languageUndefined
    Title of host publicationProceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)
    Place of PublicationUtrecht
    Number of pages7
    ISBN (Print)978-90-73461-56-7
    Publication statusPublished - Nov 2008
    Event19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008 - Veldhoven, Netherlands
    Duration: 27 Nov 200828 Nov 2008
    Conference number: 19

    Publication series

    PublisherTechnologiestichting STW


    Conference19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008


    • EWI-14637
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-255021
    • EC Grant Agreement nr.: FP7/215881
    • IR-65230

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