An Automated Design-flow for FPGA-based Sequential Simulation

P.T. Wolkotte, J.H. Rutgers, P.K.F. Holzenspies, M. Westmijze, M. Westmijze, R. Blumink, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

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Abstract

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.
Original languageUndefined
Title of host publicationProceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)
Place of PublicationUtrecht
PublisherSTW
Pages126-132
Number of pages7
ISBN (Print)978-90-73461-56-7
Publication statusPublished - Nov 2008
Event19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008 - Veldhoven, Netherlands
Duration: 27 Nov 200828 Nov 2008
Conference number: 19

Publication series

Name
PublisherTechnologiestichting STW
Number2008/14935

Conference

Conference19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008
CountryNetherlands
CityVeldhoven
Period27/11/0828/11/08

Keywords

  • EWI-14637
  • CAES-EEA: Efficient Embedded Architectures
  • METIS-255021
  • EC Grant Agreement nr.: FP7/215881
  • IR-65230

Cite this

Wolkotte, P. T., Rutgers, J. H., Holzenspies, P. K. F., Westmijze, M., Westmijze, M., Blumink, R., & Smit, G. J. M. (2008). An Automated Design-flow for FPGA-based Sequential Simulation. In Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC) (pp. 126-132). Utrecht: STW.
Wolkotte, P.T. ; Rutgers, J.H. ; Holzenspies, P.K.F. ; Westmijze, M. ; Westmijze, M. ; Blumink, R. ; Smit, Gerardus Johannes Maria. / An Automated Design-flow for FPGA-based Sequential Simulation. Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). Utrecht : STW, 2008. pp. 126-132
@inproceedings{fb307994dde04757b7f59276a4616120,
title = "An Automated Design-flow for FPGA-based Sequential Simulation",
abstract = "In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.",
keywords = "EWI-14637, CAES-EEA: Efficient Embedded Architectures, METIS-255021, EC Grant Agreement nr.: FP7/215881, IR-65230",
author = "P.T. Wolkotte and J.H. Rutgers and P.K.F. Holzenspies and M. Westmijze and M. Westmijze and R. Blumink and Smit, {Gerardus Johannes Maria}",
year = "2008",
month = "11",
language = "Undefined",
isbn = "978-90-73461-56-7",
publisher = "STW",
number = "2008/14935",
pages = "126--132",
booktitle = "Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)",

}

Wolkotte, PT, Rutgers, JH, Holzenspies, PKF, Westmijze, M, Westmijze, M, Blumink, R & Smit, GJM 2008, An Automated Design-flow for FPGA-based Sequential Simulation. in Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). STW, Utrecht, pp. 126-132, 19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008, Veldhoven, Netherlands, 27/11/08.

An Automated Design-flow for FPGA-based Sequential Simulation. / Wolkotte, P.T.; Rutgers, J.H.; Holzenspies, P.K.F.; Westmijze, M.; Westmijze, M.; Blumink, R.; Smit, Gerardus Johannes Maria.

Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). Utrecht : STW, 2008. p. 126-132.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

TY - GEN

T1 - An Automated Design-flow for FPGA-based Sequential Simulation

AU - Wolkotte, P.T.

AU - Rutgers, J.H.

AU - Holzenspies, P.K.F.

AU - Westmijze, M.

AU - Westmijze, M.

AU - Blumink, R.

AU - Smit, Gerardus Johannes Maria

PY - 2008/11

Y1 - 2008/11

N2 - In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.

AB - In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.

KW - EWI-14637

KW - CAES-EEA: Efficient Embedded Architectures

KW - METIS-255021

KW - EC Grant Agreement nr.: FP7/215881

KW - IR-65230

M3 - Conference contribution

SN - 978-90-73461-56-7

SP - 126

EP - 132

BT - Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)

PB - STW

CY - Utrecht

ER -

Wolkotte PT, Rutgers JH, Holzenspies PKF, Westmijze M, Westmijze M, Blumink R et al. An Automated Design-flow for FPGA-based Sequential Simulation. In Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). Utrecht: STW. 2008. p. 126-132