In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.
|Title of host publication||Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)|
|Place of Publication||Utrecht|
|Number of pages||7|
|Publication status||Published - Nov 2008|
|Event||19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008 - Veldhoven, Netherlands|
Duration: 27 Nov 2008 → 28 Nov 2008
Conference number: 19
|Conference||19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008|
|Period||27/11/08 → 28/11/08|
- CAES-EEA: Efficient Embedded Architectures
- EC Grant Agreement nr.: FP7/215881
Wolkotte, P. T., Rutgers, J. H., Holzenspies, P. K. F., Westmijze, M., Westmijze, M., Blumink, R., & Smit, G. J. M. (2008). An Automated Design-flow for FPGA-based Sequential Simulation. In Proceedings of the 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC) (pp. 126-132). Utrecht: STW.