An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y.V. Ponomarev; P.A. Stolk; A.C.M.C. van Brandenburg; C.J.J. Dachs; M. Kaiser; A.H. Montree; R. Roes; J. Schmitz; P.H. Woerlee

doi:10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y.V. Ponomarev, P.A. Stolk, A.C.M.C. van Brandenburg, C.J.J. Dachs, M. Kaiser, A.H. Montree, R. Roes, J. Schmitz, P.H. Woerlee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

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Abstract

An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control V_T, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V_T roll-off behavior, and 67mV/dec sub-V_T voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

Original language	English
Title of host publication	1999 Symposium on VLSI Technology
Subtitle of host publication	digest of technical papers : June 14-16, 1999, Kyoto
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	65-66
Number of pages	2
ISBN (Electronic)	4-930813-94-8
ISBN (Print)	4-930813-93-X, 0-7803-5438-9
DOIs	https://doi.org/10.1109/VLSIT.1999.799342
Publication status	Published - 14 Jun 1999
Event	1999 Symposium on VLSI Technology - Kyoto, Japan Duration: 14 Jun 1999 → 16 Jun 1999

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	IEEE
Volume	1999
ISSN (Print)	0743-1562

Conference

Conference	1999 Symposium on VLSI Technology
Country/Territory	Japan
City	Kyoto
Period	14/06/99 → 16/06/99

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSIT.1999.799342

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Ponomarev, Y. V., Stolk, P. A., van Brandenburg, A. C. M. C., Dachs, C. J. J., Kaiser, M., Montree, A. H., Roes, R., Schmitz, J., & Woerlee, P. H. (1999). An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. In 1999 Symposium on VLSI Technology: digest of technical papers : June 14-16, 1999, Kyoto (pp. 65-66). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 1999). IEEE. https://doi.org/10.1109/VLSIT.1999.799342

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title = "An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications",

abstract = "An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.",

author = "Y.V. Ponomarev and P.A. Stolk and {van Brandenburg}, A.C.M.C. and C.J.J. Dachs and M. Kaiser and A.H. Montree and R. Roes and J. Schmitz and P.H. Woerlee",

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Ponomarev, YV, Stolk, PA, van Brandenburg, ACMC, Dachs, CJJ, Kaiser, M, Montree, AH, Roes, R, Schmitz, J & Woerlee, PH 1999, An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. in 1999 Symposium on VLSI Technology: digest of technical papers : June 14-16, 1999, Kyoto. Digest of Technical Papers - Symposium on VLSI Technology, vol. 1999, IEEE, Piscataway, NJ, pp. 65-66, 1999 Symposium on VLSI Technology, Kyoto, Japan, 14/06/99. https://doi.org/10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. / Ponomarev, Y.V.; Stolk, P.A.; van Brandenburg, A.C.M.C. et al.
1999 Symposium on VLSI Technology: digest of technical papers : June 14-16, 1999, Kyoto. Piscataway, NJ: IEEE, 1999. p. 65-66 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 1999).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Ponomarev YV, Stolk PA, van Brandenburg ACMC, Dachs CJJ, Kaiser M, Montree AH et al. An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications. In 1999 Symposium on VLSI Technology: digest of technical papers : June 14-16, 1999, Kyoto. Piscataway, NJ: IEEE. 1999. p. 65-66. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.1999.799342

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

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