An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y.V. Ponomarev, P.A. Stolk, A.C.M.C. van Brandenburg, C.J.J. Dachs, M. Kaiser, A.H. Montree, R. Roes, J. Schmitz, P.H. Woerlee

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)

    Abstract

    An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

    Original languageEnglish
    Title of host publication1999 Symposium on VLSI Technology
    Subtitle of host publicationdigest of technical papers : June 14-16, 1999, Kyoto
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages65-66
    Number of pages2
    ISBN (Electronic)4-930813-94-8
    ISBN (Print)4-930813-93-X, 0-7803-5438-9
    DOIs
    Publication statusPublished - 14 Jun 1999
    Event1999 Symposium on VLSI Technology - Kyoto, Japan
    Duration: 14 Jun 199916 Jun 1999

    Publication series

    NameDigest of Technical Papers - Symposium on VLSI Technology
    PublisherIEEE
    Volume1999
    ISSN (Print)0743-1562

    Conference

    Conference1999 Symposium on VLSI Technology
    CountryJapan
    CityKyoto
    Period14/06/9916/06/99

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