An Energy and Performance Exploration of Network-on-Chip Architectures

N.K. Jha (Editor), Arnab Banerjee, P.T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerardus Johannes Maria Smit

    Research output: Contribution to journalArticleAcademicpeer-review

    47 Citations (Scopus)
    151 Downloads (Pure)

    Abstract

    In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs.
    Original languageUndefined
    Article number10.1109/TVLSI.2008.2011232
    Pages (from-to)319-329
    Number of pages11
    JournalIEEE transactions on very large scale integration (VLSI) systems
    Volume17
    Issue number3
    DOIs
    Publication statusPublished - Mar 2009

    Keywords

    • low-power design
    • METIS-263784
    • Measurement
    • Network on Chip (NoC)
    • Evaluation
    • IR-65433
    • performance comparison
    • EWI-15231
    • EC Grant Agreement nr.: FP6/001908
    • Circuit-switching networks
    • Simulation
    • packet-switching networks
    • CAES-EEA: Efficient Embedded Architectures

    Cite this

    Jha, N. K. (Ed.), Banerjee, A., Wolkotte, P. T., Mullins, R. D., Moore, S. W., & Smit, G. J. M. (2009). An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE transactions on very large scale integration (VLSI) systems, 17(3), 319-329. [10.1109/TVLSI.2008.2011232]. https://doi.org/10.1109/TVLSI.2008.2011232
    Jha, N.K. (Editor) ; Banerjee, Arnab ; Wolkotte, P.T. ; Mullins, Robert D. ; Moore, Simon W. ; Smit, Gerardus Johannes Maria. / An Energy and Performance Exploration of Network-on-Chip Architectures. In: IEEE transactions on very large scale integration (VLSI) systems. 2009 ; Vol. 17, No. 3. pp. 319-329.
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    abstract = "In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs.",
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    author = "N.K. Jha and Arnab Banerjee and P.T. Wolkotte and Mullins, {Robert D.} and Moore, {Simon W.} and Smit, {Gerardus Johannes Maria}",
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    Jha, NK (ed.), Banerjee, A, Wolkotte, PT, Mullins, RD, Moore, SW & Smit, GJM 2009, 'An Energy and Performance Exploration of Network-on-Chip Architectures', IEEE transactions on very large scale integration (VLSI) systems, vol. 17, no. 3, 10.1109/TVLSI.2008.2011232, pp. 319-329. https://doi.org/10.1109/TVLSI.2008.2011232

    An Energy and Performance Exploration of Network-on-Chip Architectures. / Jha, N.K. (Editor); Banerjee, Arnab; Wolkotte, P.T.; Mullins, Robert D.; Moore, Simon W.; Smit, Gerardus Johannes Maria.

    In: IEEE transactions on very large scale integration (VLSI) systems, Vol. 17, No. 3, 10.1109/TVLSI.2008.2011232, 03.2009, p. 319-329.

    Research output: Contribution to journalArticleAcademicpeer-review

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