An energy-efficient FPGA-based convolutional neural network implementation

Hasan Irmak; Nikolaos Alachiotis; Daniel Ziener

doi:10.1109/SIU53274.2021.9477823

An energy-efficient FPGA-based convolutional neural network implementation

Hasan Irmak, Nikolaos Alachiotis, Daniel Ziener

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

933 Downloads (Pure)

Abstract

Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

Original language	English
Title of host publication	SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings
Place of Publication	Piscataway, NJ
Publisher	IEEE
ISBN (Electronic)	978-1-6654-3649-6
ISBN (Print)	978-1-6654-3650-2
DOIs	https://doi.org/10.1109/SIU53274.2021.9477823
Publication status	Published - 2021
Event	29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021 - Virtual, Istanbul, Turkey Duration: 9 Jun 2021 → 11 Jun 2021 Conference number: 29

Conference

Conference	29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021
Abbreviated title	SIU 2021
Country/Territory	Turkey
City	Virtual, Istanbul
Period	9/06/21 → 11/06/21

Keywords

2022 OA procedure
CNN
FPGA
LeNet
Accelerator

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/SIU53274.2021.9477823

Irmak2021energy-efficientFinal published version, 475 KBLicence: Taverne

Cite this

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title = "An energy-efficient FPGA-based convolutional neural network implementation",

abstract = "Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.",

keywords = "2022 OA procedure, CNN, FPGA, LeNet, Accelerator",

author = "Hasan Irmak and Nikolaos Alachiotis and Daniel Ziener",

note = "Funding Information: This research was supported by The Scientific and Technological Research Council of Turkey (TUBITAK). Publisher Copyright: {\textcopyright} 2021 IEEE.; 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021, SIU 2021 ; Conference date: 09-06-2021 Through 11-06-2021",

year = "2021",

doi = "10.1109/SIU53274.2021.9477823",

language = "English",

isbn = "978-1-6654-3650-2",

booktitle = "SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings",

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Irmak, H, Alachiotis, N & Ziener, D 2021, An energy-efficient FPGA-based convolutional neural network implementation. in SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings., 9477823, IEEE, Piscataway, NJ, 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021, Virtual, Istanbul, Turkey, 9/06/21. https://doi.org/10.1109/SIU53274.2021.9477823

An energy-efficient FPGA-based convolutional neural network implementation. / Irmak, Hasan; Alachiotis, Nikolaos; Ziener, Daniel.
SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings. Piscataway, NJ: IEEE, 2021. 9477823.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An energy-efficient FPGA-based convolutional neural network implementation

AU - Irmak, Hasan

AU - Alachiotis, Nikolaos

AU - Ziener, Daniel

N1 - Conference code: 29

PY - 2021

Y1 - 2021

N2 - Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

AB - Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

KW - 2022 OA procedure

KW - CNN

KW - FPGA

KW - LeNet

KW - Accelerator

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DO - 10.1109/SIU53274.2021.9477823

M3 - Conference contribution

AN - SCOPUS:85111416634

SN - 978-1-6654-3650-2

BT - SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings

PB - IEEE

CY - Piscataway, NJ

T2 - 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021

Y2 - 9 June 2021 through 11 June 2021

ER -

An energy-efficient FPGA-based convolutional neural network implementation

Abstract

Conference

Keywords

UN SDGs

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