An energy-efficient FPGA-based convolutional neural network implementation

Hasan Irmak, Nikolaos Alachiotis, Daniel Ziener

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

Original languageEnglish
Title of host publicationSIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings
Place of PublicationPiscataway, NJ
PublisherIEEE
ISBN (Electronic)978-1-6654-3649-6
ISBN (Print)978-1-6654-3650-2
DOIs
Publication statusPublished - 2021
Event29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021 - Virtual, Istanbul, Turkey
Duration: 9 Jun 202111 Jun 2021

Conference

Conference29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021
CountryTurkey
CityVirtual, Istanbul
Period9/06/2111/06/21

Keywords

  • Accelerator
  • CNN
  • FPGA
  • LeNet

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