An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

N.K. Kavaldjiev; G.J.M. Smit

doi:10.1109/DSD.2004.1333317

An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

N.K. Kavaldjiev, G.J.M. Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial implementation results for a network router show its feasibility and size comparable with other available solutions.

Original language	English
Title of host publication	Euromicro Symposium on Digital System Design, DSD 2004
Place of Publication	Los Alamitos, CA
Publisher	IEEE
Pages	492-498
Number of pages	7
ISBN (Print)	0-7695-2203-3
DOIs	https://doi.org/10.1109/DSD.2004.1333317
Publication status	Published - Sept 2004
Event	7th EUROMICRO Symposium on Digital System Design, DSD 2004 - Rennes, France Duration: 31 Aug 2004 → 3 Sept 2004 Conference number: 7

Conference

Conference	7th EUROMICRO Symposium on Digital System Design, DSD 2004
Abbreviated title	DSD
Country/Territory	France
City	Rennes
Period	31/08/04 → 3/09/04

Keywords

CAES-EEA: Efficient Embedded Architectures
2023 OA procedure

Access to Document

10.1109/DSD.2004.1333317

ArticleFinal published version, 914 KBLicence: Taverne

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An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip
Kavaldjiev, N. K. & Smit, G. J. M., Jun 2004, Enschede: Centre for Telematics and Information Technology (CTIT). 7 p. (CTIT technical report series; no. TR-CTIT-04-25)
Research output: Book/Report › Report › Other research output

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Cite this

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abstract = "This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial implementation results for a network router show its feasibility and size comparable with other available solutions.",

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AB - This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial implementation results for a network router show its feasibility and size comparable with other available solutions.

KW - CAES-EEA: Efficient Embedded Architectures

KW - 2023 OA procedure

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DO - 10.1109/DSD.2004.1333317

M3 - Conference contribution

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BT - Euromicro Symposium on Digital System Design, DSD 2004

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Y2 - 31 August 2004 through 3 September 2004

ER -

An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

Abstract

Conference

Keywords

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Research output

An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

Cite this