An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

P.T. Wolkotte; Gerardus Johannes Maria Smit; G.K. Rauwerda; L.T. Smit

doi:10.1109/IPDPS.2005.95

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

P.T. Wolkotte, Gerardus Johannes Maria Smit, G.K. Rauwerda, L.T. Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

139 Citations (Scopus)

354 Downloads (Pure)

Abstract

Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 μm technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalent.

Original language	Undefined
Title of host publication	Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005)
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE Computer Society
Pages	155
Number of pages	8
ISBN (Print)	0-7695-2312-9
DOIs	https://doi.org/10.1109/IPDPS.2005.95
Publication status	Published - Apr 2005
Event	12th Reconfigurable Architectures Workshop, RAW 2005 - Denver, United States Duration: 4 Apr 2005 → 5 Apr 2005 Conference number: 12 http://www.ece.lsu.edu/vaidy/raw05/

Publication series

Name
Publisher	IEEE Computer Society

Conference

Conference	12th Reconfigurable Architectures Workshop, RAW 2005
Abbreviated title	RAW
Country/Territory	United States
City	Denver
Period	4/04/05 → 5/04/05
Internet address	http://www.ece.lsu.edu/vaidy/raw05/

Keywords

IR-54746
EWI-1479
CAES-EEA: Efficient Embedded Architectures
EC Grant Agreement nr.: FP6/001908
METIS-229212

Access to Document

10.1109/IPDPS.2005.95

http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.95

Cite this

Wolkotte, P. T., Smit, G. J. M., Rauwerda, G. K., & Smit, L. T. (2005). An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip. In Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005) (pp. 155). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2005.95

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abstract = "Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 μm technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalent.",

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Wolkotte, PT, Smit, GJM, Rauwerda, GK & Smit, LT 2005, An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip. in Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005). IEEE Computer Society, Los Alamitos, CA, USA, pp. 155, 12th Reconfigurable Architectures Workshop, RAW 2005, Denver, Colorado, United States, 4/04/05. https://doi.org/10.1109/IPDPS.2005.95

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip. / Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Rauwerda, G.K. et al.

Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005). Los Alamitos, CA, USA : IEEE Computer Society, 2005. p. 155.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Wolkotte, P.T.

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N2 - Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 μm technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalent.

AB - Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 μm technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalent.

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BT - Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005)

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CY - Los Alamitos, CA, USA

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