An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Harijot Singh Bindra, Anne J. Annema, S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Bram Nauta

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    A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.
    Original languageEnglish
    Title of host publicationESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
    Place of PublicationLeuven, Belgium
    Number of pages238
    ISBN (Electronic)978-1-5090-5025-3
    ISBN (Print)978-1-5090-5026-0
    Publication statusPublished - 13 Sept 2017


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