An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Harijot Singh Bindra; Anne J. Annema; S.M. Louwsma; Adrianus Johannes Maria van Tuijl; Bram  Nauta

An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Harijot Singh Bindra, Anne J. Annema, S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

15 Downloads (Pure)

Abstract

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

Original language	English
Title of host publication	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Place of Publication	Leuven, Belgium
Publisher	IEEE
Pages	235
Number of pages	238
ISBN (Electronic)	978-1-5090-5025-3
ISBN (Print)	978-1-5090-5026-0
Publication status	Published - 13 Sept 2017

Cite this

@inproceedings{7dbbb27e0e8d4320924d77e689bb6638,

title = "An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC",

abstract = "A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.",

author = "Bindra, {Harijot Singh} and Annema, {Anne J.} and S.M. Louwsma and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2017",

month = sep,

day = "13",

language = "English",

isbn = "978-1-5090-5026-0 ",

pages = "235",

booktitle = "ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference",

publisher = "IEEE",

address = "United States",

}

TY - GEN

T1 - An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

AU - Bindra, Harijot Singh

AU - Annema, Anne J.

AU - Louwsma, S.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

PY - 2017/9/13

Y1 - 2017/9/13

N2 - A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

AB - A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

UR - http://ieeexplore.ieee.org/document/8094569/

M3 - Conference contribution

SN - 978-1-5090-5026-0

SP - 235

BT - ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

PB - IEEE

CY - Leuven, Belgium

ER -

An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Abstract

Other files and links

Fingerprint

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Low Energy Design Techniques For Data Converters

A 30fJ/comparison dynamic bias comparator

Cite this