An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Harijot Singh Bindra; Anne J. Annema; S.M. Louwsma; Adrianus Johannes Maria van Tuijl; Bram  Nauta

doi:10.1109/ESSCIRC.2017.8094569

An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Harijot Singh Bindra
, Anne J. Annema
, S.M. Louwsma
, Adrianus Johannes Maria van Tuijl
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

55 Downloads (Pure)

Abstract

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

Original language	English
Title of host publication	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Place of Publication	Leuven, Belgium
Publisher	IEEE
Pages	235
Number of pages	238
ISBN (Electronic)	978-1-5090-5025-3
ISBN (Print)	978-1-5090-5026-0
DOIs	https://doi.org/10.1109/ESSCIRC.2017.8094569
Publication status	Published - 13 Sept 2017

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10.1109/ESSCIRC.2017.8094569

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9 Citations
2 Conference contribution
1 PhD Thesis - Research UT, graduation UT

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply
Bindra, H. S., Annema, A. J., Wienk, G. J. M., Nauta, B. & Louwsma, S., 17 Apr 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA: IEEE, 8780150. (Proceedings of the Custom Integrated Circuits Conference; vol. 2019-April).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
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Low Energy Design Techniques For Data Converters
Bindra, H. S., 13 Nov 2019, Enschede: University of Twente. 163 p.
Research output: Thesis › PhD Thesis - Research UT, graduation UT

Open Access
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A 30fJ/comparison dynamic bias comparator
Bindra, H. S., Lokin, C. E., Annema, A. J. & Nauta, B., 12 Sept 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference . Leuven, Belgium: IEEE, p. 71-74 4 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
File
51 Link opens in a new tab Citations (Scopus)

2096 Downloads (Pure)

Cite this

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title = "An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC",

abstract = "A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.",

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AU - Bindra, Harijot Singh

AU - Annema, Anne J.

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AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

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N2 - A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

AB - A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

U2 - 10.1109/ESSCIRC.2017.8094569

DO - 10.1109/ESSCIRC.2017.8094569

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BT - ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

PB - IEEE

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An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Abstract

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Research output

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Low Energy Design Techniques For Data Converters

A 30fJ/comparison dynamic bias comparator

Cite this