An indirect technique for estimating reliability of analog and mixed-signal systems during operational life

M.A. Khan; Hans G. Kerkhoff

doi:10.1109/DDECS.2013.6549809

An indirect technique for estimating reliability of analog and mixed-signal systems during operational life

M.A. Khan, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

68 Downloads (Pure)

Abstract

Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

Original language	Undefined
Title of host publication	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE
Pages	159-164
Number of pages	6
ISBN (Print)	978-1-4673-6135-4
DOIs	https://doi.org/10.1109/DDECS.2013.6549809
Publication status	Published - 8 Apr 2013
Event	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013 - Karlovy Vary, Czech Republic Duration: 8 Apr 2013 → 10 Apr 2013 Conference number: 16 http://www.fit.vutbr.cz/events/ddecs2013/about.php?section=about http://www.ddecs.org/

Publication series

Name
Publisher	IEEE

Conference

Conference	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013
Abbreviated title	DDECS
Country/Territory	Czech Republic
City	Karlovy Vary
Period	8/04/13 → 10/04/13
Internet address	http://www.fit.vutbr.cz/events/ddecs2013/about.php?section=about http://www.ddecs.org/

Keywords

CAES-TDT: Testable Design and Test
offset voltage
input signal monitoring
temperature monitoring
METIS-300089
EWI-23840
Reliability
IR-87491
time before failure

Access to Document

10.1109/DDECS.2013.6549809

06549809

Cite this

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title = "An indirect technique for estimating reliability of analog and mixed-signal systems during operational life",

abstract = "Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.",

keywords = "CAES-TDT: Testable Design and Test, offset voltage, input signal monitoring, temperature monitoring, METIS-300089, EWI-23840, Reliability, IR-87491, time before failure",

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year = "2013",

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language = "Undefined",

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booktitle = "16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013",

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Khan, MA & Kerkhoff, HG 2013, An indirect technique for estimating reliability of analog and mixed-signal systems during operational life. in 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013. IEEE, Los Alamitos, CA, USA, pp. 159-164, 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, 8/04/13. https://doi.org/10.1109/DDECS.2013.6549809

An indirect technique for estimating reliability of analog and mixed-signal systems during operational life. / Khan, M.A.; Kerkhoff, Hans G.
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013. Los Alamitos, CA, USA: IEEE, 2013. p. 159-164.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - An indirect technique for estimating reliability of analog and mixed-signal systems during operational life

AU - Khan, M.A.

AU - Kerkhoff, Hans G.

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PY - 2013/4/8

Y1 - 2013/4/8

N2 - Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

AB - Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

KW - CAES-TDT: Testable Design and Test

KW - offset voltage

KW - input signal monitoring

KW - temperature monitoring

KW - METIS-300089

KW - EWI-23840

KW - Reliability

KW - IR-87491

KW - time before failure

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DO - 10.1109/DDECS.2013.6549809

M3 - Conference contribution

SN - 978-1-4673-6135-4

SP - 159

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BT - 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013

PB - IEEE

CY - Los Alamitos, CA, USA

T2 - 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013

Y2 - 8 April 2013 through 10 April 2013

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