Abstract
Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.
Original language | Undefined |
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Title of host publication | 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013 |
Place of Publication | Los Alamitos, CA, USA |
Publisher | IEEE |
Pages | 159-164 |
Number of pages | 6 |
ISBN (Print) | 978-1-4673-6135-4 |
DOIs | |
Publication status | Published - 8 Apr 2013 |
Event | 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013 - Karlovy Vary, Czech Republic Duration: 8 Apr 2013 → 10 Apr 2013 Conference number: 16 http://www.fit.vutbr.cz/events/ddecs2013/about.php?section=about http://www.ddecs.org/ |
Publication series
Name | |
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Publisher | IEEE |
Conference
Conference | 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013 |
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Abbreviated title | DDECS |
Country/Territory | Czech Republic |
City | Karlovy Vary |
Period | 8/04/13 → 10/04/13 |
Internet address |
Keywords
- CAES-TDT: Testable Design and Test
- offset voltage
- input signal monitoring
- temperature monitoring
- METIS-300089
- EWI-23840
- Reliability
- IR-87491
- time before failure