An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process

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    Abstract

    In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.
    Original languageEnglish
    Title of host publicationProceedings of the 39th European Solid State Circuits Conference, ESSCIRC 2013
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages89-92
    Number of pages4
    ISBN (Print)978-1-4799-0643-7
    DOIs
    Publication statusPublished - 17 Sep 2013
    Event39th European Solid‐State Circuits Conference, ESSCIRC 2013 - Bucharest, Romania
    Duration: 16 Sep 201320 Sep 2013
    Conference number: 39

    Publication series

    NameProceedings European Solid State Circuits Conference, ESSCIRC
    PublisherIEEE
    Volume2013
    ISSN (Print)1930-8833

    Conference

    Conference39th European Solid‐State Circuits Conference, ESSCIRC 2013
    Abbreviated titleESSCIRC
    CountryRomania
    CityBucharest
    Period16/09/1320/09/13

    Keywords

    • EWI-23834
    • METIS-302543
    • IR-88760

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