Abstract
In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.
Original language | English |
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Title of host publication | Proceedings of the 39th European Solid State Circuits Conference, ESSCIRC 2013 |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 89-92 |
Number of pages | 4 |
ISBN (Print) | 978-1-4799-0643-7 |
DOIs | |
Publication status | Published - 17 Sept 2013 |
Event | 39th European Solid‐State Circuits Conference, ESSCIRC 2013 - Bucharest, Romania Duration: 16 Sept 2013 → 20 Sept 2013 Conference number: 39 |
Publication series
Name | Proceedings European Solid State Circuits Conference, ESSCIRC |
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Publisher | IEEE |
Volume | 2013 |
ISSN (Print) | 1930-8833 |
Conference
Conference | 39th European Solid‐State Circuits Conference, ESSCIRC 2013 |
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Abbreviated title | ESSCIRC |
Country/Territory | Romania |
City | Bucharest |
Period | 16/09/13 → 20/09/13 |
Keywords
- EWI-23834
- METIS-302543
- IR-88760