An Integrated Circuit Provided with a Fail-Safe Mode

Anne J. Annema (Inventor), G.J.G.M. Geelen (Inventor)

Research output: PatentProfessional

Original languageUndefined
Patent numberWO-00111777
Priority date15/02/01
Publication statusIn preparation - 15 Feb 2001

Keywords

  • METIS-202775

Cite this

Annema, A. J., & Geelen, G. J. G. M. (2001). An Integrated Circuit Provided with a Fail-Safe Mode. Manuscript in preparation. (Patent No. WO-00111777).
Annema, Anne J. (Inventor) ; Geelen, G.J.G.M. (Inventor). / An Integrated Circuit Provided with a Fail-Safe Mode. Patent No.: WO-00111777.
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title = "An Integrated Circuit Provided with a Fail-Safe Mode",
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author = "Annema, {Anne J.} and G.J.G.M. Geelen",
year = "2001",
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Annema, AJ & Geelen, GJGM 2001, An Integrated Circuit Provided with a Fail-Safe Mode, Patent No. WO-00111777.

An Integrated Circuit Provided with a Fail-Safe Mode. / Annema, Anne J. (Inventor); Geelen, G.J.G.M. (Inventor).

Patent No.: WO-00111777.

Research output: PatentProfessional

TY - PAT

T1 - An Integrated Circuit Provided with a Fail-Safe Mode

AU - Annema, Anne J.

AU - Geelen, G.J.G.M.

PY - 2001/2/15

Y1 - 2001/2/15

KW - METIS-202775

M3 - Patent

M1 - WO-00111777

ER -

Annema AJ, Geelen GJGM, inventors. An Integrated Circuit Provided with a Fail-Safe Mode. WO-00111777. 2001 Feb 15.