An interleaved full nyquist high-speed DAC technique

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    A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 below 50 dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these sub-DACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04 mm2 while consuming 110 mW from a single 1.0 V supply.
    Original languageEnglish
    Pages (from-to)704-713
    Number of pages10
    JournalIEEE journal of solid-state circuits
    Issue number3
    Publication statusPublished - 1 Mar 2015


    • EWI-25931
    • IR-95613
    • METIS-312550


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