An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS

S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Maarten Vertregt, Peter C.S. Scholtens, Bram Nauta

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    A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.
    Original languageUndefined
    Title of host publicationthe 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004)
    Place of PublicationUtrecht
    Number of pages5
    ISBN (Print)90-73461-43-X
    Publication statusPublished - Nov 2004
    Event15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands
    Duration: 25 Nov 200426 Nov 2004
    Conference number: 15

    Publication series

    PublisherSTW Technology Foundation


    Conference15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004
    Abbreviated titleProRisc


    • Jitter
    • interleaving
    • track and hold
    • sample and hold
    • EWI-14497
    • METIS-221474
    • IR-49274
    • AD-converter

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