A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.
|Title of host publication||the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004)|
|Place of Publication||Utrecht|
|Number of pages||5|
|Publication status||Published - Nov 2004|
|Event||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands|
Duration: 25 Nov 2004 → 26 Nov 2004
Conference number: 15
|Publisher||STW Technology Foundation|
|Conference||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004|
|Period||25/11/04 → 26/11/04|
- track and hold
- sample and hold
Louwsma, S. M., van Tuijl, A. J. M., Vertregt, M., Scholtens, P. C. S., & Nauta, B. (2004). An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS. In the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004) (pp. 546-550). Utrecht: STW.