An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS

S.M. Louwsma; Adrianus Johannes Maria van Tuijl; Maarten Vertregt; Peter C.S. Scholtens; Bram Nauta

An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS

S.M. Louwsma
, Adrianus Johannes Maria van Tuijl
, Maarten Vertregt
, Peter C.S. Scholtens
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

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Abstract

A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.

Original language	Undefined
Title of host publication	the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004)
Place of Publication	Utrecht
Publisher	STW
Pages	546-550
Number of pages	5
ISBN (Print)	90-73461-43-X
Publication status	Published - Nov 2004
Event	15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands Duration: 25 Nov 2004 → 26 Nov 2004 Conference number: 15

Publication series

Name
Publisher	STW Technology Foundation

Conference

Conference	15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004
Abbreviated title	ProRisc
Country/Territory	Netherlands
City	Veldhoven
Period	25/11/04 → 26/11/04

Keywords

Jitter
interleaving
track and hold
sample and hold
EWI-14497
METIS-221474
IR-49274
AD-converter

Access to Document

Cite this

@inproceedings{4b6772c6357142eca67af50fe2988c11,

title = "An Interleaving Track \& Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS",

abstract = "A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.",

keywords = "Jitter, interleaving, track and hold, sample and hold, EWI-14497, METIS-221474, IR-49274, AD-converter",

author = "S.M. Louwsma and \{van Tuijl\}, \{Adrianus Johannes Maria\} and Maarten Vertregt and Scholtens, \{Peter C.S.\} and Bram Nauta",

note = "isbn nr van CD-rom: 90-73461-43-X ; 15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 ; Conference date: 25-11-2004 Through 26-11-2004",

year = "2004",

month = nov,

language = "Undefined",

isbn = "90-73461-43-X",

publisher = "STW",

pages = "546--550",

booktitle = "the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004)",

}

Louwsma, SM, van Tuijl, AJM, Vertregt, M, Scholtens, PCS & Nauta, B 2004, An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS. in the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004). STW, Utrecht, pp. 546-550, 15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004, Veldhoven, Netherlands, 25/11/04.

TY - GEN

T1 - An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS

AU - Louwsma, S.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Vertregt, Maarten

AU - Scholtens, Peter C.S.

AU - Nauta, Bram

N1 - Conference code: 15

PY - 2004/11

Y1 - 2004/11

N2 - A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.

AB - A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 mm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.

KW - Jitter

KW - interleaving

KW - track and hold

KW - sample and hold

KW - EWI-14497

KW - METIS-221474

KW - IR-49274

KW - AD-converter

M3 - Conference contribution

SN - 90-73461-43-X

SP - 546

EP - 550

BT - the 15th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2004)

PB - STW

CY - Utrecht

T2 - 15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004

Y2 - 25 November 2004 through 26 November 2004

ER -