An online soft error mitigation technique for control logic of VLIW processors

The soft error phenomenon is forecast to be a real threat for today’s technology of ICs. While implementing error detection and correction codes for regular structural memory arrays have been effectively used to stem the emerging soft error threat, utilizing a low overhead approach for the complex and unstructured control logic of modern processors is still a challenge. This paper presents a low overhead reliability enhancement scheme for the control logic of a Very Large Instruction Word (VLIW) processor. First, a soft error sensitivity analysis has been carried out in order to distinguish the most vulnerable signals inside the control unit. Subsequently, these vulnerable control signals have been classified into either an opcode-dependent or instruction-dependent control signal. The strategy for protecting opcode-dependent control signals utilizes a ROM memory, while instruction-dependent control signals are protected using a RAM memory as a cache to store a history of these control signals along with the Triple Modular Redundancy concept to mask the single transient faults. This technique has been implemented on a high-performance processor, the Xentium processor, in order to validate its degree of fault tolerance and performance overhead as well.