Abstract
Digital down conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algorithm consists of two simple cascading integrating comb (CIC) filters and a finite input response (FIR) filter preceded by a modulator that is controlled with a numeric controlled oscillator (NCO). Implementations of the algorithm have been made for five architectures, two application specific integrated circuits (ASIC), a general purpose processor (GPP), a field programmable gate array (FPGA), and the Montium tile processor (TP). All architectures are functionally capable of performing the algorithm. The differences between the architectures are their performance, flexibility and energy consumption. In this paper, we compared the energy consumption of the architectures when performing the DDC algorithm. The ASIC is the best solution if digital down conversion is constantly required. When digital down conversion is needed only parts of the time, the Altera Cyclone II is the best solution due to its smaller technology size. In the spare time, the reconfigurable architectures can be reconfigured for other tasks of today's multimedia devices.
Original language | Undefined |
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Title of host publication | Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS'06) - 12th Reconfigurable Architecture Workshop (RAW 2006) |
Place of Publication | Los Alamitos, CA, USA |
Publisher | IEEE Computer Society |
Pages | 192-200 |
Number of pages | 8 |
ISBN (Print) | 1-4244-0054-6 |
DOIs | |
Publication status | Published - Apr 2006 |
Event | 13th Reconfigurable Architectures Workshop, RAW 2006 - Rhodes Island, Greece Duration: 25 Apr 2006 → 26 Apr 2006 Conference number: 13 http://www.ece.lsu.edu/vaidy/raw06/ |
Publication series
Name | |
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Publisher | IEEE Computer Society |
Number | 06EX1521 |
Workshop
Workshop | 13th Reconfigurable Architectures Workshop, RAW 2006 |
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Abbreviated title | RAW |
Country/Territory | Greece |
City | Rhodes Island |
Period | 25/04/06 → 26/04/06 |
Internet address |
Keywords
- EC Grant Agreement nr.: FP6/001908
- EWI-8099
- IR-66589
- METIS-237591
- CAES-EEA: Efficient Embedded Architectures