An Optimal Architecture for a DDC

T. Bijlsma, P.T. Wolkotte, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)
    85 Downloads (Pure)

    Abstract

    Digital down conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algorithm consists of two simple cascading integrating comb (CIC) filters and a finite input response (FIR) filter preceded by a modulator that is controlled with a numeric controlled oscillator (NCO). Implementations of the algorithm have been made for five architectures, two application specific integrated circuits (ASIC), a general purpose processor (GPP), a field programmable gate array (FPGA), and the Montium tile processor (TP). All architectures are functionally capable of performing the algorithm. The differences between the architectures are their performance, flexibility and energy consumption. In this paper, we compared the energy consumption of the architectures when performing the DDC algorithm. The ASIC is the best solution if digital down conversion is constantly required. When digital down conversion is needed only parts of the time, the Altera Cyclone II is the best solution due to its smaller technology size. In the spare time, the reconfigurable architectures can be reconfigured for other tasks of today's multimedia devices.
    Original languageUndefined
    Title of host publicationProceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS'06) - 12th Reconfigurable Architecture Workshop (RAW 2006)
    Place of PublicationLos Alamitos, CA, USA
    PublisherIEEE Computer Society
    Pages192-200
    Number of pages8
    ISBN (Print)1-4244-0054-6
    DOIs
    Publication statusPublished - Apr 2006
    Event13th Reconfigurable Architectures Workshop, RAW 2006 - Rhodes Island, Greece
    Duration: 25 Apr 200626 Apr 2006
    Conference number: 13
    http://www.ece.lsu.edu/vaidy/raw06/

    Publication series

    Name
    PublisherIEEE Computer Society
    Number06EX1521

    Workshop

    Workshop13th Reconfigurable Architectures Workshop, RAW 2006
    Abbreviated titleRAW
    CountryGreece
    CityRhodes Island
    Period25/04/0626/04/06
    Internet address

    Keywords

    • EC Grant Agreement nr.: FP6/001908
    • EWI-8099
    • IR-66589
    • METIS-237591
    • CAES-EEA: Efficient Embedded Architectures

    Cite this

    Bijlsma, T., Wolkotte, P. T., & Smit, G. J. M. (2006). An Optimal Architecture for a DDC. In Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS'06) - 12th Reconfigurable Architecture Workshop (RAW 2006) (pp. 192-200). [10.1109/IPDPS.2006.1639440] Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/IPDPS.2006.1639440