An Optimal Variable-Latency Architecture for Deterministic Approaches to Stochastic Computing with Unary Bit Stream Preserving Properties

Classical Stochastic Computing methods perform operations on bit streams generated using random number generators. Sufficient accuracy requires long bit streams which leads to very high latency and larger area. Deterministic approaches to Stochastic Computing greatly reduce the latency and area, and produce fully accurate results, but still have high latency. While state-of-the-art variable-latency architectures show an up to 70% reduction in latency, they still perform operations that do not contribute to the final result. In this paper we present an optimal variable-latency archi-tecture in terms of minimum required cycles to obtain fully accurate results. We propose an efficient stochastic number gen-erator that uses a down counter and compare-to-zero hardware compared to an up counter and binary comparator. This key contribution means that the latency of our design only depends on the magnitude of input values and is independent of the number of bits or inputs used. This is not the case in state-of-the-art variable-latency architectures. Also, unlike any other architecture, ours preserves the unary bit stream encoding after performing additions and multiplications, which enables more complex designs that require unary bit streams such as sorting. Our architecture thereby further improves the area, latency, and energy efficiency compared to the state-of-the-art.