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An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
Bruno Endres Forlin*, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis, Marco Ottavi
*Corresponding author for this work
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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