Analog Circuits in Ultra-Deep Sub-Micron CMOS

Anne J. Annema, Bram Nauta, Ronald van Langevelde, Hans Tuinhout

    Research output: Contribution to journalArticleAcademicpeer-review

    309 Citations (Scopus)
    123 Downloads (Pure)

    Abstract

    Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.
    Original languageEnglish
    Pages (from-to)132-143
    Number of pages12
    JournalIEEE journal of solid-state circuits
    Volume40
    Issue number1
    DOIs
    Publication statusPublished - 2005

    Keywords

    • Breakdown
    • CMOS
    • Analog design
    • Distortion
    • Low power
    • Low voltage
    • Scaling
    • UDSM
    • gate leakage
    • future performance
    • Technology
    • mismatch
    • METIS-224177
    • IR-52564
    • Evolution

    Fingerprint

    Dive into the research topics of 'Analog Circuits in Ultra-Deep Sub-Micron CMOS'. Together they form a unique fingerprint.

    Cite this