Analog CMOS computational circuits

Klaas Bult, Hans Wallinga

    Research output: Contribution to conferencePaper

    1 Citation (Scopus)
    16 Downloads (Pure)

    Abstract

    A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.
    Original languageUndefined
    Pages119-121
    Publication statusPublished - 1986

    Keywords

    • IR-96391

    Cite this

    Bult, K., & Wallinga, H. (1986). Analog CMOS computational circuits. 119-121.
    Bult, Klaas ; Wallinga, Hans. / Analog CMOS computational circuits.
    @conference{ae43f4a7eefe430d81c88ac1b12114c6,
    title = "Analog CMOS computational circuits",
    abstract = "A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8{\%} at an output current of 80{\%} of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28{\%} at an output current of 120{\%} of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.",
    keywords = "IR-96391",
    author = "Klaas Bult and Hans Wallinga",
    year = "1986",
    language = "Undefined",
    pages = "119--121",

    }

    Bult, K & Wallinga, H 1986, 'Analog CMOS computational circuits' pp. 119-121.

    Analog CMOS computational circuits. / Bult, Klaas; Wallinga, Hans.

    1986. 119-121.

    Research output: Contribution to conferencePaper

    TY - CONF

    T1 - Analog CMOS computational circuits

    AU - Bult, Klaas

    AU - Wallinga, Hans

    PY - 1986

    Y1 - 1986

    N2 - A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

    AB - A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

    KW - IR-96391

    M3 - Paper

    SP - 119

    EP - 121

    ER -

    Bult K, Wallinga H. Analog CMOS computational circuits. 1986.