A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.
|Publication status||Published - 1986|
|Event||12th European Solid-State Circuits Conference, ESSCIRC 1986 - Delft, Netherlands|
Duration: 16 Sep 1986 → 18 Sep 1986
Conference number: 12
|Conference||12th European Solid-State Circuits Conference, ESSCIRC 1986|
|Period||16/09/86 → 18/09/86|