Analog CMOS computational circuits

Klaas Bult, Hans Wallinga

    Research output: Contribution to conferencePaper

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    Abstract

    A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.
    Original languageEnglish
    Pages119-121
    DOIs
    Publication statusPublished - 1986
    Event12th European Solid-State Circuits Conference, ESSCIRC 1986 - Delft, Netherlands
    Duration: 16 Sep 198618 Sep 1986
    Conference number: 12

    Conference

    Conference12th European Solid-State Circuits Conference, ESSCIRC 1986
    Abbreviated titleESSCIRC
    CountryNetherlands
    CityDelft
    Period16/09/8618/09/86

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