### Abstract

A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

Original language | English |
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Pages | 119-121 |

DOIs | |

Publication status | Published - 1986 |

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## Cite this

Bult, K., & Wallinga, H. (1986).

*Analog CMOS computational circuits*. 119-121. https://doi.org/10.1109/ESSCIRC.1986.5468339