Analog CMOS computational circuits

Klaas Bult; Hans Wallinga

doi:10.1109/ESSCIRC.1986.5468339

Analog CMOS computational circuits

Klaas Bult, Hans Wallinga

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Abstract

A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

Original language	English
Pages	119-121
DOIs	https://doi.org/10.1109/ESSCIRC.1986.5468339
Publication status	Published - 1986
Event	12th European Solid-State Circuits Conference, ESSCIRC 1986 - Delft, Netherlands Duration: 16 Sept 1986 → 18 Sept 1986 Conference number: 12

Conference

Conference	12th European Solid-State Circuits Conference, ESSCIRC 1986
Abbreviated title	ESSCIRC
Country/Territory	Netherlands
City	Delft
Period	16/09/86 → 18/09/86

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10.1109/ESSCIRC.1986.5468339

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title = "Analog CMOS computational circuits",

abstract = "A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.",

author = "Klaas Bult and Hans Wallinga",

year = "1986",

doi = "10.1109/ESSCIRC.1986.5468339",

language = "English",

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note = "12th European Solid-State Circuits Conference, ESSCIRC 1986, ESSCIRC ; Conference date: 16-09-1986 Through 18-09-1986",

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T1 - Analog CMOS computational circuits

AU - Bult, Klaas

AU - Wallinga, Hans

N1 - Conference code: 12

PY - 1986

Y1 - 1986

N2 - A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

AB - A new CMOS three transistor current squaring circuit is proposed. The versatility of the circuit is shown in three applications: an eight transistor four-quadrant current multiplier/divider circuit with a THD of less than 0.8% at an output current of 80% of the bias current, a floating input linear V-I convertor with variable transconductance and a THD of less than 0.28% at an output current of 120% of the bias current and a bandwidth of above 5 Mhz, and a four-quadrant voltage multiplier.

U2 - 10.1109/ESSCIRC.1986.5468339

DO - 10.1109/ESSCIRC.1986.5468339

M3 - Paper

SP - 119

EP - 121

T2 - 12th European Solid-State Circuits Conference, ESSCIRC 1986

Y2 - 16 September 1986 through 18 September 1986

ER -

Analog CMOS computational circuits

Abstract

Conference

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