Analog test interface for IEEE 1687 employing split SAR architecture to support embedded instrument dependability applications

Jerrin Pathrose, Leon Van De Logt, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Embedded instruments have become ubiquitous in modern day System-on-Chips for test and monitoring purposes. IEEE 1687 or IJTAG addresses the standardization of access and operation of these embedded instruments. Recently, there has been a lot of interest in employing embedded instruments for dependability purposes. Many of these embedded instruments are required to monitor physical quantities which are analog in nature. A cost-effective architecture to integrate these analog instruments into the IEEE 1687 infrastructure is a bottleneck and has not yet been standardized. This paper presents a time and area efficient architecture to interface analog embedded instruments onto the IEEE 1687 network especially for dependability applications. The architecture mitigates the drawbacks associated with utilizing an analog test bus and enables periodic sampling with minimal hardware overhead. The simulations to illustrate the concept have been conducted with TSMC 40nm CMOS technology.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
PublisherIEEE
ISBN (Electronic)9781728122601
DOIs
Publication statusPublished - Oct 2019
Event32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands
Duration: 2 Oct 20194 Oct 2019
Conference number: 32

Conference

Conference32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
Abbreviated titleDFT 2019
Country/TerritoryNetherlands
CityNoordwijk
Period2/10/194/10/19

Keywords

  • Analog Test Bus
  • Embedded Instrument
  • IEEE 1687
  • Monitoring

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