Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)
    576 Downloads (Pure)

    Abstract

    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.
    Original languageEnglish
    Title of host publication Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005)
    Place of PublicationGrenoble, France
    PublisherIEEE Computer Society
    Pages45-54
    Number of pages10
    ISBN (Print)0780392051
    DOIs
    Publication statusPublished - Sep 2005
    Event31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France
    Duration: 12 Sep 200516 Sep 2005
    Conference number: 31

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference31st European Solid-State Circuits Conference, ESSCIRC 2005
    Abbreviated titleESSCIRC
    CountryFrance
    CityGrenoble
    Period12/09/0516/09/05

    Fingerprint

    Networks (circuits)
    Electric potential
    Transistors
    Defects
    Oxides

    Keywords

    • IR-54684
    • METIS-229033
    • EWI-14519

    Cite this

    Nauta, B., & Annema, A. J. (2005). Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies. In Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005) (pp. 45-54). Grenoble, France: IEEE Computer Society. https://doi.org/10.1109/ESSCIR.2005.1541556
    Nauta, Bram ; Annema, Anne J. / Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies. Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble, France : IEEE Computer Society, 2005. pp. 45-54
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    title = "Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies",
    abstract = "CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.",
    keywords = "IR-54684, METIS-229033, EWI-14519",
    author = "Bram Nauta and Annema, {Anne J.}",
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    Nauta, B & Annema, AJ 2005, Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies. in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005). IEEE Computer Society, Grenoble, France, pp. 45-54, 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSCIR.2005.1541556

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies. / Nauta, Bram; Annema, Anne J.

    Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble, France : IEEE Computer Society, 2005. p. 45-54.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    AB - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

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    Nauta B, Annema AJ. Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies. In Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005). Grenoble, France: IEEE Computer Society. 2005. p. 45-54 https://doi.org/10.1109/ESSCIR.2005.1541556