Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

Bram Nauta; Anne J. Annema

doi:10.1109/ESSCIR.2005.1541556

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

Original language	English
Title of host publication	Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005)
Place of Publication	Grenoble, France
Publisher	IEEE
Pages	45-54
Number of pages	10
ISBN (Print)	0780392051
DOIs	https://doi.org/10.1109/ESSCIR.2005.1541556
Publication status	Published - Sept 2005
Event	31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France Duration: 12 Sept 2005 → 16 Sept 2005 Conference number: 31

Publication series

Name
Publisher	IEEE

Conference

Conference	31st European Solid-State Circuits Conference, ESSCIRC 2005
Abbreviated title	ESSCIRC
Country/Territory	France
City	Grenoble
Period	12/09/05 → 16/09/05

Keywords

IR-54684
METIS-229033
EWI-14519

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10.1109/ESSCIR.2005.1541556

01541556Final published version, 218 KB

Cite this

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title = "Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies",

abstract = "CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.",

keywords = "IR-54684, METIS-229033, EWI-14519",

author = "Bram Nauta and Annema, \{Anne J.\}",

note = "Keynote presentation; 31st European Solid-State Circuits Conference, ESSCIRC 2005, ESSCIRC ; Conference date: 12-09-2005 Through 16-09-2005",

year = "2005",

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doi = "10.1109/ESSCIR.2005.1541556",

language = "English",

isbn = "0780392051",

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pages = "45--54",

booktitle = "Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005)",

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T1 - Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

AU - Nauta, Bram

AU - Annema, Anne J.

N1 - Conference code: 31

PY - 2005/9

Y1 - 2005/9

N2 - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

AB - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

KW - IR-54684

KW - METIS-229033

KW - EWI-14519

U2 - 10.1109/ESSCIR.2005.1541556

DO - 10.1109/ESSCIR.2005.1541556

M3 - Conference contribution

SN - 0780392051

SP - 45

EP - 54

BT - Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC 2005)

PB - IEEE

CY - Grenoble, France

T2 - 31st European Solid-State Circuits Conference, ESSCIRC 2005

Y2 - 12 September 2005 through 16 September 2005

ER -

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

Abstract

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Keywords

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